I have a query on Timer interrupt for OMAP3530.
I have enabled the timer interrupt for RTOS which i use. I get the
Timer Interrupt as per expected behaviour. At this point of time the
Interrupt bit and IRQ Pending in the interrupt controller seems to be
set.
Now after handling the interrupt I clear the Interrupt by writing to
Interrupt status register (This is said in spec.) Now i find that
Interrupt bit and IRQ Pending in the interrupt controller is reset ,
showing that the interrupt is handled.
Now the problem: Even though i have cleared the timer interrupt i keep
on getting the Timer interrupt.This is not a desired behaviour as i
have configured for One shot timer interrupt. After the first
interrupt the timer is stoped. What might be the problem ?
Important Note: When i single step through my OS i do not get the
timer interrupt again and again.The execution seems to be perfect when
i single step .
But when i say run it goes and hit at the break point which i have put
it in IRQ vector.
Can u help me ? How is GP Timer handled in Uboot. or linux?
Now the problem: Even though i have cleared the timer interrupt i keep
on getting the Timer interrupt.This is not a desired behaviour as i
have configured for One shot timer interrupt. After the first
interrupt the timer is stoped. What might be the problem ?
Important Note: When i single step through my OS i do not get the
timer interrupt again and again.The execution seems to be perfect when
i single step .
But when i say run it goes and hit at the break point which i have put
it in IRQ vector.
Hi Rahanesh,
From your email it seems, like you miss to set the NEWIRQAGR bit in
INTCPS_CONTROL after processing the interrupt. More info about this can be
found in the TRM (spruf98b.pdf) chapter 10 - Especially figure 10.5 and
table 10-16... Without doing this, AFAIR the IRQ-output from the
Interrupt-controller will stay active causing the ARM to always jump to the
INTR-vector, even though no interrupt source is active...
With respect to the stuff working different when you single-step. This is
because emulation as default (using Lauterbach and Code Composer Studio)
will prevent interrupts from happening unless you hit "Run" as you as well
found. The reason for this is to prevent single-stepping being mixed up in
ISRs all the time. The assumption being, that if you are allowed to
single-step that particular piece of your code, you can as well live without
interrupts occurring.
Here you should however take special care, since if you hit step-over on a
function call in the C-environment, what the debugger will do is usually to
set a breakpoint at the next statement and let the core free running (in
order to speed up the execution). In this case you will therefore get an
interrupt although you would expect it to behave as being in
"single-stepping mode"...
I’m very interested in your FreeRTOS port !!! Please stay in touch !!!
I am currently looking at building my own kernel on the beagleboard with the help of Think (http://think.objectweb.org/)
It is a set of tools to build component based embedded systems.
I would be very great full if you could share your timer code with me since I’m not an expert in low level programming and that might save me some time
I am very happy for your interest. The name of the RTOS is RoSES.
RoSES is completely designed and developed by TATA ELXSI Ltd.
It is not an Open source RTOS. I will not be able to share my code as such.
But I will be very happy to help you with configuring the timers.
I would like to trigger an interrupt on the board from an external
source, but really have no idea where to begin.
Hi Rahanesh?
First of all - Please send emails/questions to the BegaleBoard mailing list
and *not* directly to me directly for the future - I can't service all
individual requests...
In order to trigger an interrupt on a GPIO from the expansion connector you
need to do the following
1) Make sure the PIN on the OMAP is set/muxed to GPIO mode (TRM Chapter 7)
2) Configure the given pin in the GPIO controller (TRM Chapter 24)
3) Enable the GPIO-block interrupt in the interrupt controller (TRM
Chapter 10)
There might be handles in Linux to do some of this - I unfortunately don't
know...
I'm new to the BB and I've only had my board for a few weeks now and
I'm trying to understand the Expansion Header/GPIO/Interrupts. I can't
seem to find any tutorials or any extensive information on this
subject?
I would like to trigger my board to turn on/wake from sleep when
triggered by an external sensor (through an interrupt, if that works
best). Can anyone point me in the right direction or suggest the best
method for triggering?
the interrupts are enabled ( cpsr: 0x8000011 ) and my handler is loaded to 0x4020fff8. I have setup a break point to my handler but I never reach it.
Can you please tell me what do I miss? I have also pasted the two structures I am using
struct InterruptController
{
unsigned char res1[0x10];
unsigned int intcSysConfig;
unsigned int intcSysStatus;
unsigned int intcSirIrq;
unsigned int intcSirFiq;
unsigned int intcControl;
unsigned int intcProtection;
unsigned int intcIdle;
unsigned int intcIrqPriority;
unsigned int intcFiqPriority;
unsigned int intcThreshold;
unsigned int intcItr0;
unsigned int intcMir0;
unsigned int intcMirClear0;
unsigned int intcMirSet0;
unsigned int intcIsrSet0;
unsigned int intcIsrClear0;
unsigned int intcPendingIrq0;
unsigned int intcPendingFiq0;
unsigned int intcItr1;
unsigned int intcMir1;
unsigned int intcMirClear1;
unsigned int intcMirSet1;
unsigned int intcIsrSet1;
unsigned int intcIsrClear1;
unsigned int intcPendingIrq1;
unsigned int intcPendingFiq1;
unsigned int intcItr2;
unsigned int intcMir2;
unsigned int intcMirClear2;
unsigned int intcMirSet2;
unsigned int intcIsrSet2;
unsigned int intcIsrClear2;
unsigned int intcPendingIrq2;
unsigned int intcPendingFiq2; // 0xDC
unsigned char res2[0x22];
unsigned int intcIlr0; // 0x100
<…rest of intcllrX registers… >
and
struct gptimer {
int tidr; /* 0x00 r /
char res[0xc];
int tiocp_cfg; / 0x10 rw /
int tistat; / 0x14 r /
int tisr; / 0x18 rw /
int tier; / 0x1c rw /
int twer; / 0x20 rw /
int tclr; / 0x24 rw /
int tcrr; / 0x28 rw /
int tldr; / 0x2c rw /
int ttgr; / 0x30 rw /
int twpc; / 0x34 r*/
int tmar; /* 0x38 rw*/
int tcar1; /* 0x3c r /
int tcicr; / 0x40 rw /
int tcar2; / 0x44 r */
};
