Hi!
I’m porting Beagleboard u-boot to a similar platform and found one thing which I consider weird. In u-boot DRAM timings are set for 165MHz and 200MHz DDR, however RAS width is different for these two memories. What is the relationship between timings and physical structure of memory? It is explicitly stated that the RAS width is 14 for both -5ns and -6ns cycle times.
Can anybody explain this?