UART clock on Debian 13 5.10.168-ti-r83

General Discussion
1

On this BBB I see 26 MHz instead of 24 MHz:

root@BB-DEB13-510:~# uname -a
Linux BB-DEB13-510 5.10.168-ti-r83 #1trixie SMP PREEMPT Thu Aug 7 20:35:21 UTC 2                                                           025 armv7l GNU/Linux
root@BB-DEB13-510:~# dmesg | grep clock
[    0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segm                                                           ent@200000/target-module@31000
[    0.000012] sched_clock: 32 bits at 26MHz, resolution 38ns, wraps every 82595                                                           524588ns
[    0.008071] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, ma                                                           x_idle_ns: 73510017198 ns
[    0.018039] TI gptimer clockevent: 26000000 Hz at /ocp/interconnect@48000000/                                                           segment@0/target-module@40000
[    0.216974] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ma                                                           x_idle_ns: 7645041785100000 ns
[    2.140992] PTP clock support registered
[    2.170571] clocksource: Switched to clocksource dmtimer
[    6.212119] omap_rtc 44e3e000.rtc: setting system clock to 2025-12-04T09:58:0                                                           8 UTC (1764842288)
root@BB-DEB13-510:~#

UART outbound data rates are 10% too low, e.g. 115200 is ~104700 (measured), 3692000 (48/13) is 3425000 (measured). Inbound data generate frame errors. Which makes no sense when the base clock is high, but nevertheless it is what it is. No changes to device tree or system were made. Clock tree is much different from Debian 12 5.10, though PER M2 div4 and UART base clk is shown as 48 MHz. I have made devmem reads to UART registers and all are set correctly.

2

The setting isn’t hiding in DT somewhere, is it?

3

Is this a clone or an official bbb? Look at the sysboot pins SYSBOOT[15:14] which set 24mhz osc.

Since these pins are on the Cape headers, remove your cape and retest..

Regards,

4

Thanks for hinting, this is a genuine board.

Your are right, without cape it is 24 MHz indeed. The cape has UART5 RTS/CTS on pins p8.31/32, though until SYSRESETN it is spec’d to be tristate.

Is there a reference of SYSBOOT pin functions? UART5 has TX/RX on SYSBOOT [8:9] p8.37/38. Is that endangering something, too?

5

There’s a big faq in the system reference manual… Do not pull up or pull down sysboot pins on power up

6

Ok, found table Figure 39 in SRM Rev. B now, that says [15:14] 01 => 24 MHz, 11 => 26 MHz.

Figure 38, though, shows all pins connected to a 100k/100k voltage divider. Then it says “S2 is used to change the level of one bit from HI to LO which changes the boot order.” How are all these 1s and 0s in Figure 38 generated?

Can 26 MHz make the UARTs clock run slow?

7

From the week pull up’s and pull down’s already on the BBB PCB… S2 is a switch that just changes the pull-up/pull-down..

Regards,