Using SPI in a kernel module

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21

First, a lot of thanks for the pointer, that could really help.

What I really want to accomplish is to get at least a medium bandwidth interface

between the LAN and some real-time data aquisition units. The LAN side is

patterned after my Agilent 89441A vector signal analyzer. You simply open

port 5025 on 192.169.178.111 and dump/read there GPIB/IEEE488-like commands &

data streams. That side seems to work, although there is not yet much flesh

to it since the data collection side is still missing.

First I wanted to try the SPI interface, then the 16 bit multiplexed bus

to get an intelligent register interface to some FPGA.

For the SPI, I decided to attach a LT2500-32 ADC; that can do 1 Msample

at 24 bits. Add FFTW in the BBB and you have a respectable Fourier analyzer.

For the hardware, that’s all that is needed:

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The Xilinx Coolrunner2 generates the sampling clock from the 100 MHz crystal osc. and collects

some left-over gates. $1.50 or so. The other small board is the ADC, its regulators and reference.

Home-etched and soldered. :slight_smile: It’s completely open, in case someone wants it.

The SPI has soaked up much more time than I had planned. A new Debian image from

Robert and some other insights at least made that I don’t get a bus error for each SPI access.

One gets thankful for small advances… At least I can now create and start PRU programs,

talk to them via the shared RAM and transfer huge data blocks to Linux virtual memory land

through ping-pong buffers. It’s just that I can’t make the SPI say a word. Verbatim. :frowning:

I also can finger the SPI pins when I re-assign them to the PRU and use R30/R31.

I also have a Red Pitaya. I like it architecture-wise, except that I’ll need a larger FPGA

to support fast ADCs with JESDI204B ports - and that it is based on that exotic Alpine Linux.

FPGAs are a home game for me, I’ve used them since there has been Xilinx.

best regards,

Gerhard

22

Hi Gerhard,
Maybe this 2 points helps for the Problem “bus errors”:

I had the same Problems at the standard Starterware mcspi, if I forget “McSPI0ModuleClkConfig” in my Setup.

I found this tip " /* check CM_PER enable status, or it may caue “Bus error” signal message. */" in https://stackoverflow.com/questions/46677025/add-chip-select-hold-time-to-beaglebone-spi .

To the tip of John “Starterware in Pru”: https://github.com/kiran4399/starterware_PRU
All spi code is the same as standard Starterware mcspi.

best wishes
Peter

23

You might be interested in the FPGA design solutions from Analog Devices. They have FPGA designs for many of their high speed data acquisition devices.

BTW, if you selected an ADC with a FIFO, then you could do the SPI comms in Linux using DMA, so there would be no need for PRU.

24

Actually , I have write a driver based on iMX6 and V850 , implement via tty driver .

And suggest you follow kernel driver ifx6x60.c

Regards

25

I mean you should follow the ifx6x60c driver struct . use tty driver as general out and input .

Dont’ use sys_open .