Weekly Progress Report: Low-latency I/O RISC-V CPU core in FPGA fabric

Google Summer of Code
21

Week 10 Updates:

  • Added IO controller module to handle GPIOs that will be mapped to x30 and x31 registers of the register file within the CPU.
  • Tested the above mentioned setup through basic simulations, still to be tested on BeagleV-Fire.
  • Wrote a TCL script for converting a normal hex file to Intel-hex format to initialize program memory at boot.
  • Based on discussion with @Vedant_Paranjape it was decided to use CLang and LLVM to cross-compile program for the softcore.

Blockers:

  • no issues this week.

Next Goals:

  • Complete the hardware testing of CPU.
  • Have a stable setup for cross-compilation of program
22

Week 11 Updates:

  • Based on repeated simulations, 2 main problems were identified.
    – Data was being received from the memory 1 clock cycle after sending the read signal and address, but the wrapper module was trying to read it in the same cycle, thus previous instruction was being read.
    – The IOs were not correctly mapped to registers.
  • A sequential logic was added to the wrapper module to read data in the next clock cycle after the read signal and address were received.
  • Performed a few modifications on the register mapping IO to map them to registers and access them correctly with correct addresses and signals.

Blockers:
As mentioned above the two issues were the blockers this week.

Next Goal:

  • Setup cross compiler.
  • APB write interface for CSR.
23

Week 12 Updates:

  • The Softcore CPU is now completely operational on BeagleV-Fire hardware.
  • APB registers are successfully applied and integrated as CSRs that can reset the Softcore and be used to transfer GPIO access to the Linux on the BVF RISCV Subsystem by just writing to the CSR.

Officially this GSOC project will end on 26th of August, but I’ll still keep working on this project.

My next goal would be to have the compiler setup and easy user access to the Softcore along with good documentation of examples, usage, and benchmarks.