diff -purN codegoogle/x-load/board/omap3530beagle/omap3530beagle.c 500/x-load/board/omap3530beagle/omap3530beagle.c
--- codegoogle/x-load/board/omap3530beagle/omap3530beagle.c	2008-03-12 12:06:14.000000000 +0530
+++ 500/x-load/board/omap3530beagle/omap3530beagle.c	2008-04-23 14:53:36.000000000 +0530
@@ -138,7 +138,7 @@ u32 wait_on_value(u32 read_bit_mask, u32
 /*********************************************************************
  * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
  *********************************************************************/
-void config_3430sdram_ddr(void)
+void config_3430sdram_ddr_133(void)
 {
    /* reset sdrc controller */
         __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
@@ -172,7 +172,7 @@ void config_3430sdram_ddr(void)
 
 }
 
-void config_3430sdram_ddr_working(void)
+void config_3430sdram_ddr(void)
 {
         /* reset sdrc controller */
         __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
@@ -189,12 +189,14 @@ void config_3430sdram_ddr_working(void)
         (*(unsigned int*)0x6D000080) = 0x02584099;//from Micron
 
         /* SDRC_ACTIM_CTRLA0 register */
-        (*(unsigned int*)0x6D00009c) = 0xa29db4c6;// for 166M
+//our value        (*(unsigned int*)0x6D00009c) = 0xa29db4c6;// for 166M
+        (*(unsigned int*)0x6D00009c) = 0xaa9db4c6;// for 166M from rkw
 
         /* SDRC_ACTIM_CTRLB0 register */
 //from micron   (*(unsigned int*)0x6D0000a0) = 0x12214;// for 166M
 
-        (*(unsigned int*)0x6D0000a0) = 0x00011417;
+//        (*(unsigned int*)0x6D0000a0) = 0x00011417; our value
+        (*(unsigned int*)0x6D0000a0) = 0x00011517;
 
         /* SDRC_RFR_CTRL0 register */
 //from micron   (*(unsigned int*)0x6D0000a4) =0x54601; // for 166M
@@ -321,6 +323,8 @@ void prcm_init(void)
 		clk_index = sys_clkin_sel;
 	}
 
+	sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
+
 	/* The DPLL tables are defined according to sysclk value and
 	 * silicon revision. The clk_index value will be used to get
 	 * the values for that input sysclk from the DPLL param table
@@ -336,11 +340,15 @@ void prcm_init(void)
 	/* Getting the base address of Core DPLL param table */
 	dpll_param_p = (dpll_param *) get_core_dpll_param();
 	/* Moving it to the right sysclk and ES rev base */
-	dpll_param_p = dpll_param_p + 2 * clk_index + sil_index;
+	dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
 	/* CORE DPLL */
 	/* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
 	sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
 	wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
+
+	 /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
+	work. write another value and then default value. */
+	sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1);     /* m3x2 */
 	sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2);	/* m3x2 */
 	sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2);	/* Set M2 */
 	sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m);	/* Set M */
@@ -376,8 +384,10 @@ void prcm_init(void)
 
 	/* Getting the base address to MPU DPLL param table */
 	dpll_param_p = (dpll_param *) get_mpu_dpll_param();
+
 	/* Moving it to the right sysclk and ES rev base */
-	dpll_param_p = dpll_param_p + 2 * clk_index + sil_index;
+	dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
+
 	/* MPU DPLL (unlocked already) */
 	sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2);	/* Set M2 */
 	sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m);	/* Set M */
@@ -389,7 +399,7 @@ void prcm_init(void)
 	/* Getting the base address to IVA DPLL param table */
 	dpll_param_p = (dpll_param *) get_iva_dpll_param();
 	/* Moving it to the right sysclk and ES rev base */
-	dpll_param_p = dpll_param_p + 2 * clk_index + sil_index;
+	dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
 	/* IVA DPLL (set to 12*20=240MHz) */
 	sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
 	wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
diff -purN codegoogle/x-load/include/configs/omap3530beagle.h 500/x-load/include/configs/omap3530beagle.h
--- codegoogle/x-load/include/configs/omap3530beagle.h	2008-03-12 11:30:26.000000000 +0530
+++ 500/x-load/include/configs/omap3530beagle.h	2008-04-03 17:46:50.000000000 +0530
@@ -71,8 +71,8 @@
 #define V_SCLK                   V_OSCK
 #endif
 
-#define PRCM_CLK_CFG2_266MHZ   1    /* VDD2=1.15v - 133MHz DDR */
-//#define PRCM_CLK_CFG2_332MHZ     1    /* VDD2=1.15v - 166MHz DDR */
+//#define PRCM_CLK_CFG2_266MHZ   1    /* VDD2=1.15v - 133MHz DDR */
+#define PRCM_CLK_CFG2_332MHZ     1    /* VDD2=1.15v - 166MHz DDR */
 #define PRCM_PCLK_OPP2           1    /* ARM=381MHz - VDD1=1.20v */
 
 /* Memory type */
