From 980fa452ed630dfa4f841ab0e1a990e9ec5e1d3d Mon Sep 17 00:00:00 2001 From: Manikandan Pillai Date: Mon, 18 Aug 2008 14:24:13 +0530 Subject: [PATCH] NAND compilation fixes taken from Beagle for OMAP3EVM Signed-off-by: Manikandan Pillai --- board/omap3evm/nand.c | 73 +++++++++++++++++++++--------------------------- 1 files changed, 32 insertions(+), 41 deletions(-) diff --git a/board/omap3evm/nand.c b/board/omap3evm/nand.c index 2f94684..d140ae0 100644 --- a/board/omap3evm/nand.c +++ b/board/omap3evm/nand.c @@ -44,33 +44,31 @@ volatile unsigned long gpmc_cs_base_add; /* * omap_nand_hwcontrol - Set the address pointers corretly for the * following address/data/command operation - * @mtd: MTD device structure - * @ctrl: Says whether Address or Command or Data is following. */ -static void omap_nand_hwcontrol(struct mtd_info *mtd, int ctrl) +static void omap_nand_hwcontrol(struct mtd_info *mtd, int cmd, + unsigned int ctrl) { register struct nand_chip *this = mtd->priv; /* Point the IO_ADDR to DATA and ADDRESS registers instead of chip address */ switch (ctrl) { - case NAND_CTL_SETCLE: + case NAND_CTRL_CHANGE | NAND_CTRL_CLE: this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD; this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; break; - case NAND_CTL_SETALE: + case NAND_CTRL_CHANGE | NAND_CTRL_ALE: this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_ADR; this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; break; - case NAND_CTL_CLRCLE: - this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; - this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; - break; - case NAND_CTL_CLRALE: + case NAND_CTRL_CHANGE | NAND_NCE: this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; break; } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); } /* @@ -79,10 +77,8 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int ctrl) * is ready again. * @mtd: MTD device structure * @chip: nand_chip structure - * @state: State from which wait function is being called i.e write/erase. */ -static int omap_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, - int state) +static int omap_nand_wait(struct mtd_info *mtd, struct nand_chip *chip) { register struct nand_chip *this = mtd->priv; int status = 0; @@ -277,8 +273,7 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode) __raw_writel(val, GPMC_BASE + GPMC_ECC_CONFIG); } -static struct nand_oobinfo hw_nand_oob_64 = { - .useecc = MTD_NANDECC_AUTOPLACE, +static struct nand_ecclayout hw_nand_oob_64 = { .eccbytes = 12, .eccpos = { 2, 3, 4, 5, @@ -287,8 +282,7 @@ static struct nand_oobinfo hw_nand_oob_64 = { .oobfree = { {20, 50} } /* don't care */ }; -static struct nand_oobinfo sw_nand_oob_64 = { - .useecc = MTD_NANDECC_AUTOPLACE, +static struct nand_ecclayout sw_nand_oob_64 = { .eccbytes = 24, .eccpos = { 40, 41, 42, 43, 44, 45, 46, 47, @@ -302,36 +296,33 @@ void omap_nand_switch_ecc(struct mtd_info *mtd, int hardware) struct nand_chip *nand = mtd->priv; if (!hardware) { - nand->eccmode = NAND_ECC_SOFT; - nand->autooob = &sw_nand_oob_64; - nand->eccsize = 256; /* set default eccsize */ - nand->eccbytes = 3; - nand->eccsteps = 8; - nand->enable_hwecc = 0; - nand->calculate_ecc = nand_calculate_ecc; - nand->correct_data = nand_correct_data; + nand->ecc.mode = NAND_ECC_SOFT; + nand->ecc.layout = &sw_nand_oob_64; + nand->ecc.size = 256; /* set default eccsize */ + nand->ecc.bytes = 3; + nand->ecc.steps = 8; + nand->ecc.hwctl = 0; + nand->ecc.calculate = nand_calculate_ecc; + nand->ecc.correct = nand_correct_data; } else { - nand->eccmode = NAND_ECC_HW3_512; - nand->autooob = &hw_nand_oob_64; - nand->eccsize = 512; - nand->eccbytes = 3; - nand->eccsteps = 4; - nand->enable_hwecc = omap_enable_hwecc; - nand->correct_data = omap_correct_data; - nand->calculate_ecc = omap_calculate_ecc; + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = &hw_nand_oob_64; + nand->ecc.size = 512; + nand->ecc.bytes = 3; + nand->ecc.steps = 4; + nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.correct = omap_correct_data; + nand->ecc.calculate = omap_calculate_ecc; omap_hwecc_init(nand); } - mtd->eccsize = nand->eccsize; - nand->oobdirty = 1; - if (nand->options & NAND_BUSWIDTH_16) { - mtd->oobavail = mtd->oobsize - (nand->autooob->eccbytes + 2); - if (nand->autooob->eccbytes & 0x01) + mtd->oobavail = mtd->oobsize - (nand->ecc.layout->eccbytes + 2); + if (nand->ecc.layout->eccbytes & 0x01) mtd->oobavail--; } else - mtd->oobavail = mtd->oobsize - (nand->autooob->eccbytes + 1); + mtd->oobavail = mtd->oobsize - (nand->ecc.layout->eccbytes + 1); } /* @@ -387,12 +378,12 @@ int board_nand_init(struct nand_chip *nand) nand->IO_ADDR_R = (int *) gpmc_cs_base_add + GPMC_NAND_DAT; nand->IO_ADDR_W = (int *) gpmc_cs_base_add + GPMC_NAND_CMD; - nand->hwcontrol = omap_nand_hwcontrol; + nand->cmd_ctrl = omap_nand_hwcontrol; nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR; nand->read_buf = omap_nand_read_buf; nand->write_buf = omap_nand_write_buf; - nand->eccmode = NAND_ECC_SOFT; + nand->ecc.mode = NAND_ECC_SOFT; /* if RDY/BSY line is connected to OMAP then use the omap ready * function and the generic nand_wait function which reads the * status register after monitoring the RDY/BSY line. Otherwise -- 1.5.6