Subject: [EXPERIMENTAL] ARM: OMAP3: Reconfigure PER DPLL4 to get higher pixel clock From: Dirk Behme At the moment, peripheral DPLL4 configuration results in max. pixel clock of 72MHz. With this, we are not able to do 1280 x 1024 >= 50Hz refresh. To be able to get >= 50Hz refresh, we need pixel clock ~76MHz. Some DPLL4 math: * Existing timing: DPLL4 CLKOUTX2: (26MHz x 2 x 0xD8) / (0xC + 1) = 864MHz PRM_96M_ALWON_CLK: 864MHz / 9 = 96MHz CM_CLKSEL1_EMU: 864MHz / 3 = 288MHz CM_CLKSEL_CAM: 864MHz / 4 = 216MHz CM_CLKSEL_DSS-tv: 864MHz / 16 = 54MHz CM_CLKSEL_DSS-dss1: 864MHz / 2 = 432MHz DSS1_ALWON_FCLK (max: 173MHz): 432MHz / 3 = 144MHz Pixel clock (max): 144MHz / 2 = 72MHz * New timing: DPLL4 CLKOUTX2: (26MHz x 2 x 0xA2) / (0xC + 1) = 648MHz PRM_96M_ALWON_CLK: 648MHz / 7 = 92.57MHz CM_CLKSEL1_EMU: 648MHz / 3 = 216MHz CM_CLKSEL_CAM: 648MHz / 3 = 216MHz CM_CLKSEL_DSS-tv: 648MHz / 12 = 54MHz CM_CLKSEL_DSS-dss1: 648MHz / 2 = 324MHz DSS1_ALWON_FCLK (max: 173MHz): 324MHz / 1 = 162MHz Pixel clock (max): 162MHz / 2 = 81MHz ATTENTION: With this PRM_96M_ALWON_CLK isn't 96MHz any more! Not sure if users of PRM_96M_ALWON_CLK can be configured to use other 96MHz clock ignoring PRM_96M_ALWON_CLK. If not, this patch can't be used if peripherals needing 96MHz PRM_96M_ALWON_CLK should be used, too. Which peripherals use PRM_96M_ALWON_CLK and can't be configured to different 96MHz clock? Signed-off-by: Dirk Behme --- ATTENTION: This is an experimental patch. It breaks PRM_96M_ALWON_CLK. Don't apply! cpu/omap3/lowlevel_init.S | 2 +- include/asm-arm/arch-omap3/clocks_omap3.h | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) Index: u-boot_steve/cpu/omap3/lowlevel_init.S =================================================================== --- u-boot_steve.orig/cpu/omap3/lowlevel_init.S +++ u-boot_steve/cpu/omap3/lowlevel_init.S @@ -348,7 +348,7 @@ per_dpll_param: .word 0xE1,0x09,0x07,0x09 /* 26MHz */ -.word 0xD8,0x0C,0x07,0x09 +.word 0xA2,0x0C,0x07,0x07 /* 38.4MHz */ .word 0xE1,0x13,0x07,0x09 Index: u-boot_steve/include/asm-arm/arch-omap3/clocks_omap3.h =================================================================== --- u-boot_steve.orig/include/asm-arm/arch-omap3/clocks_omap3.h +++ u-boot_steve/include/asm-arm/arch-omap3/clocks_omap3.h @@ -41,10 +41,10 @@ # define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ /* PER DPLL */ -# define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ -# define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ -# define PER_M4X2 2 /* 432MHz : CM_CLKSEL_DSS-dss1 */ -# define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ +# define PER_M6X2 3 /* 216MHz: CM_CLKSEL1_EMU */ +# define PER_M5X2 3 /* 216MHz: CM_CLKSEL_CAM */ +# define PER_M4X2 2 /* 324MHz : CM_CLKSEL_DSS-dss1 */ +# define PER_M3X2 12 /* 54MHz : CM_CLKSEL_DSS-tv */ # define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50))