Index: uboot_beagle/board/omap3530beagle/clock.c =================================================================== --- uboot_beagle.orig/board/omap3530beagle/clock.c +++ uboot_beagle/board/omap3530beagle/clock.c @@ -1,8 +1,8 @@ /* * (C) Copyright 2008 * Texas Instruments, - * - * Author : + * + * Author : * Sunil Kumar * Shashi Ranjan * @@ -31,33 +31,17 @@ #include #include #include +#include #include #include #include #include #include -/* Used to index into DPLL parameter tables */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -}; - -typedef struct dpll_param dpll_param; - -/* Following functions are exported from lowlevel_init.S */ - -extern dpll_param *get_mpu_dpll_param(void); -extern dpll_param *get_iva_dpll_param(void); -extern dpll_param *get_core_dpll_param(void); -extern dpll_param *get_per_dpll_param(void); - -/************************************************************* - * get_sys_clk_speed - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *************************************************************/ +/****************************************************************************** + * get_sys_clk_speed() - determine reference oscillator speed + * based on known 32kHz clock and gptimer. + *****************************************************************************/ u32 get_osc_clk_speed(void) { u32 start, cstart, cend, cdiff, val; @@ -80,14 +64,15 @@ u32 get_osc_clk_speed(void) __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ - /* enable 32kHz source */ - /* determine sys_clk via gauging */ + /* enable 32kHz source, determine sys_clk via gauging */ start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */ - cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ - while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */ - cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ + /* get start sys_clk count */ + cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); + /* wait for 40 cycles */ + while (__raw_readl(S32K_CR) < (start + 20)) ; + cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ cdiff = cend - cstart; /* get elapsed ticks */ /* based on number of ticks assign speed */ @@ -106,11 +91,10 @@ u32 get_osc_clk_speed(void) } /****************************************************************************** - * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on - * -- input oscillator clock frequency. - * + * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on + * input oscillator clock frequency. *****************************************************************************/ -void get_sys_clkin_sel(u32 osc_clk, u32 * sys_clkin_sel) +void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) { if (osc_clk == S38_4M) *sys_clkin_sel = 4; @@ -126,22 +110,21 @@ void get_sys_clkin_sel(u32 osc_clk, u32 /****************************************************************************** * prcm_init() - inits clocks for PRCM as defined in clocks.h - * -- called from SRAM, or Flash (using temp SRAM stack). + * called from SRAM, or Flash (using temp SRAM stack). *****************************************************************************/ void prcm_init(void) { void (*f_lock_pll) (u32, u32, u32, u32); int xip_safe, p0, p1, p2, p3; u32 osc_clk = 0, sys_clkin_sel; - extern void *_end_vect, *_start; u32 clk_index, sil_index; dpll_param *dpll_param_p; - f_lock_pll = - (void *) ((u32) & _end_vect - (u32) & _start + SRAM_VECT_CODE); + f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + + SRAM_VECT_CODE); xip_safe = running_in_sram(); - + /* Gauge the input clock speed and find out the sys_clkin_sel * value corresponding to the input clock. */ @@ -162,8 +145,8 @@ void prcm_init(void) /* The DPLL tables are defined according to sysclk value and * silicon revision. The clk_index value will be used to get * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. + * and sil_index will get the values for that SysClk for the + * appropriate silicon rev. */ sil_index = get_cpu_rev() - 1; /* Unlock MPU DPLL (slows things down, and needed later) */ @@ -182,36 +165,37 @@ void prcm_init(void) /* For OMAP3 ES1.0 Errata 1.50, default value directly doesnt work. write another value and then default value. */ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ + sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ - sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ - sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ + sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ + sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); } else if (running_in_flash()) { - /* if running from flash, jump to small relocated code area in SRAM. */ + /* if running from flash, jump to small relocated code + area in SRAM. */ p0 = __raw_readl(CM_CLKEN_PLL); - sr32((u32) & p0, 0, 3, PLL_FAST_RELOCK_BYPASS); - sr32((u32) & p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32((u32) &p0, 0, 3, PLL_FAST_RELOCK_BYPASS); + sr32((u32) &p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */ p1 = __raw_readl(CM_CLKSEL1_PLL); - sr32((u32) & p1, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32((u32) & p1, 16, 11, dpll_param_p->m); /* Set M */ - sr32((u32) & p1, 8, 7, dpll_param_p->n); /* Set N */ - sr32((u32) & p1, 6, 1, 0); /* set source for 96M */ + sr32((u32) &p1, 27, 2, dpll_param_p->m2); /* Set M2 */ + sr32((u32) &p1, 16, 11, dpll_param_p->m); /* Set M */ + sr32((u32) &p1, 8, 7, dpll_param_p->n); /* Set N */ + sr32((u32) &p1, 6, 1, 0); /* set source for 96M */ p2 = __raw_readl(CM_CLKSEL_CORE); - sr32((u32) & p2, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32((u32) & p2, 4, 2, CORE_FUSB_DIV); /* fsusb */ - sr32((u32) & p2, 2, 2, CORE_L4_DIV); /* l4 */ - sr32((u32) & p2, 0, 2, CORE_L3_DIV); /* l3 */ + sr32((u32) &p2, 8, 4, CORE_SSI_DIV); /* ssi */ + sr32((u32) &p2, 4, 2, CORE_FUSB_DIV); /* fsusb */ + sr32((u32) &p2, 2, 2, CORE_L4_DIV); /* l4 */ + sr32((u32) &p2, 0, 2, CORE_L3_DIV); /* l3 */ p3 = CM_IDLEST_CKGEN; @@ -230,24 +214,24 @@ void prcm_init(void) /* Errata 1.50 Workaround for OMAP3 ES1.0 only */ /* If using default divisors, write default divisor + 1 and then the actual divisor value */ - /* Need to change it to silicon and revisino check */ + /* Need to change it to silicon and revision check */ if (1) { - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2 + 1); /* set M6 */ - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2 + 1); /* set M5 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2 + 1); /* set M4 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2 + 1); /* set M3 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2 + 1); /* set M2 */ - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ + sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2 + 1); /* set M6 */ + sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ + sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2 + 1); /* set M5 */ + sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ + sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2 + 1); /* set M4 */ + sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ + sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2 + 1); /* set M3 */ + sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ + sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2 + 1); /* set M2 */ + sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ } else { - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ + sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ + sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ + sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ + sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ + sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ } sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ @@ -288,10 +272,9 @@ void prcm_init(void) sdelay(5000); } -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ +/****************************************************************************** + * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...) + *****************************************************************************/ void per_clocks_enable(void) { /* Enable GP2 timer. */ @@ -316,23 +299,6 @@ void per_clocks_enable(void) /* Enable the ICLK for 32K Sync Timer as its used in udelay */ sr32(CM_ICLKEN_WKUP, 2, 1, 0x1); -#define CLOCKS_ALL_ON 1 - -#ifdef CLOCKS_ALL_ON - - #define FCK_IVA2_ON 0x00000001 - #define FCK_CORE1_ON 0x03fffe29 - #define ICK_CORE1_ON 0x3ffffffb - #define ICK_CORE2_ON 0x0000001f - #define FCK_WKUP_ON 0x000000e9 - #define ICK_WKUP_ON 0x0000003f - #define FCK_DSS_ON 0x00000005 - #define ICK_DSS_ON 0x00000001 - #define FCK_CAM_ON 0x00000001 - #define ICK_CAM_ON 0x00000001 - #define FCK_PER_ON 0x0003ffff - #define ICK_PER_ON 0x0003ffff - sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON); sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON); sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON); @@ -345,6 +311,6 @@ void per_clocks_enable(void) sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON); sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON); sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON); -#endif + sdelay(1000); } Index: uboot_beagle/include/asm-arm/arch-omap3/clocks.h =================================================================== --- uboot_beagle.orig/include/asm-arm/arch-omap3/clocks.h +++ uboot_beagle/include/asm-arm/arch-omap3/clocks.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 + * (C) Copyright 2006-2008 * Texas Instruments, * Richard Woodruff * @@ -18,10 +18,10 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef _OMAP34XX_CLOCKS_H_ -#define _OMAP34XX_CLOCKS_H_ +#ifndef _CLOCKS_H_ +#define _CLOCKS_H_ -#define LDELAY 12000000 +#define LDELAY 12000000 #define S12M 12000000 #define S13M 13000000 @@ -30,6 +30,33 @@ #define S26M 26000000 #define S38_4M 38400000 -#include +#define FCK_IVA2_ON 0x00000001 +#define FCK_CORE1_ON 0x03fffe29 +#define ICK_CORE1_ON 0x3ffffffb +#define ICK_CORE2_ON 0x0000001f +#define FCK_WKUP_ON 0x000000e9 +#define ICK_WKUP_ON 0x0000003f +#define FCK_DSS_ON 0x00000005 +#define ICK_DSS_ON 0x00000001 +#define FCK_CAM_ON 0x00000001 +#define ICK_CAM_ON 0x00000001 +#define FCK_PER_ON 0x0003ffff +#define ICK_PER_ON 0x0003ffff + +/* Used to index into DPLL parameter tables */ +typedef struct { + unsigned int m; + unsigned int n; + unsigned int fsel; + unsigned int m2; +} dpll_param; + +/* Following functions are exported from lowlevel_init.S */ +extern dpll_param *get_mpu_dpll_param(void); +extern dpll_param *get_iva_dpll_param(void); +extern dpll_param *get_core_dpll_param(void); +extern dpll_param *get_per_dpll_param(void); + +extern void *_end_vect, *_start; #endif Index: uboot_beagle/include/asm-arm/arch-omap3/clocks_omap3.h =================================================================== --- uboot_beagle.orig/include/asm-arm/arch-omap3/clocks_omap3.h +++ uboot_beagle/include/asm-arm/arch-omap3/clocks_omap3.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 + * (C) Copyright 2006-2008 * Texas Instruments, * Richard Woodruff * @@ -18,13 +18,13 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef _OMAP343X_CLOCKS_H_ -#define _OMAP343X_CLOCKS_H_ +#ifndef _CLOCKS_OMAP3_H_ +#define _CLOCKS_OMAP3_H_ -#define PLL_STOP 1 /* PER & IVA */ +#define PLL_STOP 1 /* PER & IVA */ #define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ #define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ -#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ +#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ /* The following configurations are OPP and SysClk value independant * and hence are defined here. All the other DPLL related values are @@ -55,80 +55,80 @@ # define M2_12 0x01 /* M3 of 2 */ # define M_12_ES1 0x19F -# define M_12_ES1 0x0E -# define FSL_12_ES1 0x03 -# define M2_12_ES1 0x1 /* M3 of 2 */ +# define N_12_ES1 0x0E +# define FSL_12_ES1 0x03 +# define M2_12_ES1 0x1 /* M3 of 2 */ -# define M_13 0x14C -# define N_13 0x0C +# define M_13 0x14C +# define N_13 0x0C # define FSEL_13 0x03 # define M2_13 0x01 /* M3 of 2 */ # define M_13_ES1 0x1B2 # define N_13_ES1 0x10 -# define FSL_13_ES1 0x03 +# define FSL_13_ES1 0x03 # define M2_13_ES1 0x01 /* M3 of 2 */ -# define M_19p2 0x19F -# define N_19p2 0x17 -# define FSEL_19p2 0x03 -# define M2_19p2 0x01 /* M3 of 2 */ +# define M_19p2 0x19F +# define N_19p2 0x17 +# define FSEL_19p2 0x03 +# define M2_19p2 0x01 /* M3 of 2 */ # define M_19p2_ES1 0x19F # define N_19p2_ES1 0x17 -# define FSL_19p2_ES1 0x03 -# define M2_19p2_ES1 0x01 /* M3 of 2 */ +# define FSL_19p2_ES1 0x03 +# define M2_19p2_ES1 0x01 /* M3 of 2 */ -# define M_26 0xA6 -# define N_26 0x0C -# define FSEL_26 0x07 -# define M2_26 0x01 /* M3 of 2 */ +# define M_26 0xA6 +# define N_26 0x0C +# define FSEL_26 0x07 +# define M2_26 0x01 /* M3 of 2 */ # define M_26_ES1 0x1B2 # define N_26_ES1 0x21 # define FSL_26_ES1 0x03 # define M2_26_ES1 0x01 /* M3 of 2 */ -# define M_38p4 0x19F -# define N_38p4 0x2F -# define FSEL_38p4 0x03 -# define M2_38p4 0x01 /* M3 of 2 */ +# define M_38p4 0x19F +# define N_38p4 0x2F +# define FSEL_38p4 0x03 +# define M2_38p4 0x01 /* M3 of 2 */ # define M_38p4_ES1 0x19F # define N_38p4_ES1 0x2F -# define FSL_38p4_ES1 0x03 -# define M2_38p4_ES1 0x01 /* M3 of 2 */ +# define FSL_38p4_ES1 0x03 +# define M2_38p4_ES1 0x01 /* M3 of 2 */ #elif defined(PRCM_CLK_CFG2_266MHZ) # define M_12 0x85 -# define N_12 0x05 -# define FSEL_12 0x07 -# define M2_12 0x02 /* M3 of 2 */ +# define N_12 0x05 +# define FSEL_12 0x07 +# define M2_12 0x02 /* M3 of 2 */ # define M_12_ES1 0x85 /* 0x10A */ # define N_12_ES1 0x05 /* 0x05 */ -# define FSL_12_ES1 0x07 /* 0x7 */ -# define M2_12_ES1 0x2 /* 0x2 with an M3 of 4 */ +# define FSL_12_ES1 0x07 /* 0x7 */ +# define M2_12_ES1 0x2 /* 0x2 with an M3 of 4 */ -# define M_13 0x10A -# define N_13 0x0C -# define FSEL_13 0x3 -# define M2_13 0x1 /* M3 of 2 */ +# define M_13 0x10A +# define N_13 0x0C +# define FSEL_13 0x3 +# define M2_13 0x1 /* M3 of 2 */ # define M_13_ES1 0x10A /* 0x214 */ # define N_13_ES1 0x0C /* 0xC */ -# define FSL_13_ES1 0x3 /* 0x3 */ +# define FSL_13_ES1 0x3 /* 0x3 */ # define M2_13_ES1 0x1 /* 0x2 with an M3 of 4 */ -# define M_19p2 0x115 -# define N_19p2 0x13 -# define FSEL_19p2 0x03 -# define M2_19p2 0x01 /* M3 of 2 */ +# define M_19p2 0x115 +# define N_19p2 0x13 +# define FSEL_19p2 0x03 +# define M2_19p2 0x01 /* M3 of 2 */ # define M_19p2_ES1 0x115 /* 0x299 */ # define N_19p2_ES1 0x13 /* 0x17 */ -# define FSL_19p2_ES1 0x03 /* 0x03 */ -# define M2_19p2_ES1 0x01 /* 0x2 with M3 of 4 */ +# define FSL_19p2_ES1 0x03 /* 0x03 */ +# define M2_19p2_ES1 0x01 /* 0x2 with M3 of 4 */ # define M_26 0x85 # define N_26 0x0C @@ -137,19 +137,19 @@ # define M_26_ES1 0x85 /* 0x10A */ # define N_26_ES1 0x0C /* 0xC */ -# define FSL_26_ES1 0x07 /* 0x7 */ +# define FSL_26_ES1 0x07 /* 0x7 */ # define M2_26_ES1 0x01 /* 0x2 with an M3 of 4 */ -# define M_38p4 0x11C -# define N_38p4 0x28 -# define FSEL_38p4 0x03 -# define M2_38p4 0x01 /* M3 of 2 */ +# define M_38p4 0x11C +# define N_38p4 0x28 +# define FSEL_38p4 0x03 +# define M2_38p4 0x01 /* M3 of 2 */ # define M_38p4_ES1 0x11C /* 0x299 */ # define N_38p4_ES1 0x28 /* 0x2f */ -# define FSL_38p4_ES1 0x03 /* 0x3 */ -# define M2_38p4_ES1 0x01 /* 0x2 with an M3 of 4 */ +# define FSL_38p4_ES1 0x03 /* 0x3 */ +# define M2_38p4_ES1 0x01 /* 0x2 with an M3 of 4 */ #endif -#endif /* endif _OMAP343X_CLOCKS_H_ */ +#endif /* endif _CLOCKS_OMAP3_H_ */ Index: uboot_beagle/board/omap3530beagle/lowlevel_init.S =================================================================== --- uboot_beagle.orig/board/omap3530beagle/lowlevel_init.S +++ uboot_beagle/board/omap3530beagle/lowlevel_init.S @@ -31,7 +31,7 @@ #include #include #include -#include +#include _TEXT_BASE: .word TEXT_BASE /* sdram load addr from config.mk */ Index: uboot_beagle/board/omap3530beagle/omap3530beagle.c =================================================================== --- uboot_beagle.orig/board/omap3530beagle/omap3530beagle.c +++ uboot_beagle/board/omap3530beagle/omap3530beagle.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include #include