Subject: ARM: OMAP3: Misc checkpatch cleanup From: Dirk Behme Misc checkpatch cleanup. No functional change. Signed-off-by: Dirk Behme --- Index: u-boot_steve/board/omap3/beagle/beagle.c =================================================================== --- u-boot_steve.orig/board/omap3/beagle/beagle.c +++ u-boot_steve/board/omap3/beagle/beagle.c @@ -98,7 +98,7 @@ int misc_init_r(void) *((uint *) 0x49058094) = 0x00000506; *((uint *) 0x49056094) = 0xF060F000; - return (0); + return 0; } /****************************************************************************** Index: u-boot_steve/cpu/omap3/cpu.c =================================================================== --- u-boot_steve.orig/cpu/omap3/cpu.c +++ u-boot_steve/cpu/omap3/cpu.c @@ -130,7 +130,7 @@ int cleanup_before_linux(void) l2cache_enable(); #endif - return (0); + return 0; } int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -139,7 +139,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, reset_cpu(0); /* NOTREACHED */ - return (0); + return 0; } void icache_enable(void) Index: u-boot_steve/cpu/omap3/interrupts.c =================================================================== --- u-boot_steve.orig/cpu/omap3/interrupts.c +++ u-boot_steve/cpu/omap3/interrupts.c @@ -186,7 +186,7 @@ int interrupt_init(void) reset_timer_masked(); /* init the timestamp and lastinc value */ - return (0); + return 0; } /* Index: u-boot_steve/cpu/omap3/mmc.c =================================================================== --- u-boot_steve.orig/cpu/omap3/mmc.c +++ u-boot_steve/cpu/omap3/mmc.c @@ -52,7 +52,7 @@ static block_dev_desc_t mmc_blk_dev; block_dev_desc_t *mmc_get_dev(int dev) { - return ((block_dev_desc_t *) &mmc_blk_dev); + return (block_dev_desc_t *) &mmc_blk_dev; } void twl4030_mmc_config(void) @@ -125,8 +125,7 @@ unsigned char mmc_clock_config(unsigned mmc_reg_out(OMAP_HSMMC_SYSCTL, ICE_MASK | CLKD_MASK, (val << CLKD_OFFSET) | ICE_OSCILLATE); - while ((OMAP_HSMMC_SYSCTL & ICS_MASK) == ICS_NOTREADY) { - } + while ((OMAP_HSMMC_SYSCTL & ICS_MASK) == ICS_NOTREADY) ; OMAP_HSMMC_SYSCTL |= CEN_ENABLE; return 1; @@ -167,8 +166,7 @@ unsigned char mmc_send_cmd(unsigned int { volatile unsigned int mmc_stat; - while ((OMAP_HSMMC_PSTATE & DATI_MASK) == DATI_CMDDIS) { - } + while ((OMAP_HSMMC_PSTATE & DATI_MASK) == DATI_CMDDIS) ; OMAP_HSMMC_BLK = BLEN_512BYTESLEN | NBLK_STPCNT; OMAP_HSMMC_STAT = 0xFFFFFFFF; Index: u-boot_steve/cpu/omap3/syslib.c =================================================================== --- u-boot_steve.orig/cpu/omap3/syslib.c +++ u-boot_steve/cpu/omap3/syslib.c @@ -65,8 +65,8 @@ u32 wait_on_value(u32 read_bit_mask, u32 ++i; val = __raw_readl(read_addr) & read_bit_mask; if (val == match_value) - return (1); + return 1; if (i == bound) - return (0); + return 0; } while (1); } Index: u-boot_steve/fs/jffs2/jffs2_1pass.c =================================================================== --- u-boot_steve.orig/fs/jffs2/jffs2_1pass.c +++ u-boot_steve/fs/jffs2/jffs2_1pass.c @@ -304,7 +304,8 @@ static inline void *get_node_mem_nor(u32 */ static inline void *get_fl_mem(u32 off, u32 size, void *ext_buf) { -#if (defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)) || defined(ONFIG_CMD_FLASH) +#if (defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)) || \ + defined(ONFIG_CMD_FLASH) struct mtdids *id = current_part->dev->id; #endif @@ -324,8 +325,9 @@ static inline void *get_fl_mem(u32 off, static inline void *get_node_mem(u32 off) { -#if (defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)) || defined(ONFIG_CMD_FLASH) - struct mtdids *id = current_part->dev->id; +#if (defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)) || \ + defined(ONFIG_CMD_FLASH) + struct mtdids *id = current_part->dev->id; #endif #if defined(CONFIG_CMD_FLASH) Index: u-boot_steve/include/asm-arm/arch-omap3/mux.h =================================================================== --- u-boot_steve.orig/include/asm-arm/arch-omap3/mux.h +++ u-boot_steve/include/asm-arm/arch-omap3/mux.h @@ -823,7 +823,8 @@ MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_nCS3), (IEN | PTU | EN | M4)) /*GPIO_54 (MMC1_WP)*/\ + MUX_VAL(CP(GPMC_nCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\ + /* - MMC1_WP*/\ MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\ MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*GPIO_57*/\ @@ -893,7 +894,8 @@ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ - MUX_VAL(CP(CSI2_DY1), (IDIS | PTU | EN | M4)) /*GPIO_115 (W2W_PON)*/\ + MUX_VAL(CP(CSI2_DY1), (IDIS | PTU | EN | M4)) /*GPIO_115*/\ + /* - W2W_PON*/\ /*Audio Interface */\ MUX_VAL(CP(McBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ MUX_VAL(CP(McBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ @@ -967,8 +969,10 @@ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168 (USBH_CPEN)*/\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTD | EN | M4)) /*GPIO_183 (USBH_RESET)*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\ + /* - USBH_CPEN*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTD | EN | M4)) /*GPIO_183*/\ + /* - USBH_RESET*/\ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ @@ -1010,8 +1014,10 @@ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M2)) /*MMC3_CLK*/\ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT4*/\ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M4)) /*GPIO_15 (MMC1-CD)*/\ - MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTU | EN | M4)) /*GPIO_16 (W2W_NRESET)*/\ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M4)) /*GPIO_15*/\ + /* - MMC1-CD*/\ + MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTU | EN | M4)) /*GPIO_16*/\ + /* - W2W_NRESET*/\ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\