Subject: ARM: OMAP3: Improve pixel clock workaround

From: Dirk Behme <dirk.behme@gmail.com>

Make pixel clock workaround compatible to existing code.

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>

---

Index: uboot-beagle/board/omap3530beagle/omap3530beagle.c
===================================================================
--- uboot-beagle.orig/board/omap3530beagle/omap3530beagle.c
+++ uboot-beagle/board/omap3530beagle/omap3530beagle.c
@@ -267,8 +267,6 @@ int misc_init_r(void)
 	*((uint *) 0x49058094) = 0x00000506;
 	*((uint *) 0x49056094) = 0xF060F000;
 
-	/* set clksel_tv and clksel_dss1 to DPLL4 clock divided by 1 */
-	*((uint *) 0x48004E40) = 0x00001001;
 	return (0);
 }
 
Index: uboot-beagle/include/asm-arm/arch-omap3/clocks_omap3.h
===================================================================
--- uboot-beagle.orig/include/asm-arm/arch-omap3/clocks_omap3.h
+++ uboot-beagle/include/asm-arm/arch-omap3/clocks_omap3.h
@@ -43,7 +43,7 @@
 /* PER DPLL */
 # define PER_M6X2       3	/* 288MHz: CM_CLKSEL1_EMU */
 # define PER_M5X2       4	/* 216MHz: CM_CLKSEL_CAM */
-# define PER_M4X2       9	/* 96MHz : CM_CLKSEL_DSS-dss1 */
+# define PER_M4X2       1	/* 864MHz: CM_CLKSEL_DSS-dss1 */
 # define PER_M3X2       16	/* 54MHz : CM_CLKSEL_DSS-tv */
 
 #  define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50))