From: Dirk Behme Clean up start beagle include files Signed-off-by: Dirk Behme -- Index: uboot-beagle/include/asm-arm/arch-omap3/cpu.h =================================================================== --- uboot-beagle.orig/include/asm-arm/arch-omap3/cpu.h +++ uboot-beagle/include/asm-arm/arch-omap3/cpu.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 + * (C) Copyright 2006-2008 * Texas Instruments, * * See file CREDITS for list of people who contributed to this @@ -22,9 +22,8 @@ * */ -#ifndef _OMAP34XX_CPU_H -#define _OMAP34XX_CPU_H -#include +#ifndef _CPU_H +#define _CPU_H /* Register offsets of common modules */ /* Control */ @@ -81,13 +80,18 @@ #define GPMC_ECC9_RESULT (0x220) /* GPMC Mapping */ -# define FLASH_BASE 0x10000000 /* NOR flash (aligned to 256 Meg) */ -# define FLASH_BASE_SDPV1 0x04000000 /* NOR flash (aligned to 64 Meg) */ -# define FLASH_BASE_SDPV2 0x10000000 /* NOR flash (aligned to 256 Meg) */ +# define FLASH_BASE 0x10000000 /* NOR flash, */ + /* aligned to 256 Meg */ +# define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */ + /* aligned to 64 Meg */ +# define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */ + /* aligned to 256 Meg */ # define DEBUG_BASE 0x08000000 /* debug board */ -# define NAND_BASE 0x30000000 /* NAND addr (actual size small port) */ +# define NAND_BASE 0x30000000 /* NAND addr */ + /* (actual size small port) */ # define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ -# define ONENAND_MAP 0x20000000 /* OneNand addr (actual size small port */ +# define ONENAND_MAP 0x20000000 /* OneNand addr */ + /* (actual size small port) */ /* SMS */ #define SMS_SYSCONFIG (OMAP34XX_SMS_BASE+0x10) @@ -151,7 +155,8 @@ #define TCAR1 0x3c /* r */ #define TSICR 0x40 /* rw */ #define TCAR2 0x44 /* r */ -#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */ + /* enable sys_clk NO-prescale /1 */ +#define GPT_EN ((0<<2)|BIT1|BIT0) /* Watchdog */ #define WWPS 0x34 /* r */ @@ -242,4 +247,4 @@ #define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) #define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) -#endif +#endif /* _CPU_H */ Index: uboot-beagle/include/asm-arm/arch-omap3/omap3.h =================================================================== --- uboot-beagle.orig/include/asm-arm/arch-omap3/omap3.h +++ uboot-beagle/include/asm-arm/arch-omap3/omap3.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 + * (C) Copyright 2006-2008 * Texas Instruments, * Richard Woodruff * Syed Mohammed Khasim @@ -23,23 +23,12 @@ * MA 02111-1307 USA */ -#ifndef _OMAP3430_SYS_H_ -#define _OMAP3430_SYS_H_ - -#include - -/* - * 3430 specific Section - */ +#ifndef _OMAP3_H_ +#define _OMAP3_H_ /* Stuff on L3 Interconnect */ #define SMX_APE_BASE 0x68000000 -/* L3 Firewall */ -#define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048) -#define A_READPERM0 (SMX_APE_BASE + 0x05050) -#define A_WRITEPERM0 (SMX_APE_BASE + 0x05058) - /* GPMC */ #define OMAP34XX_GPMC_BASE (0x6E000000) @@ -53,19 +42,13 @@ * L4 Peripherals - L4 Wakeup and L4 Core now */ #define OMAP34XX_CORE_L4_IO_BASE 0x48000000 - #define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000 - #define OMAP34XX_L4_PER 0x49000000 - #define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE /* CONTROL */ #define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE+0x2000) -/* TAP information dont know for 3430*/ -#define OMAP34XX_TAP_BASE (0x49000000) /*giving some junk for virtio */ - /* UART */ #define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE+0x6a000) #define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE+0x6c000) @@ -102,53 +85,47 @@ #define OMAP34XX_GPIO5_BASE 0x49056000 #define OMAP34XX_GPIO6_BASE 0x49058000 -/* - * SDP3430 specific Section - */ - -/* - * The 343x's chip selects are programmable. The mask ROM - * does configure CS0 to 0x08000000 before dispatch. So, if - * you want your code to live below that address, you have to - * be prepared to jump though hoops, to reset the base address. - * Same as in SDP3430 - */ -#if (CONFIG_3430SDP) - /* base address for indirect vectors (internal boot mode) */ #define SRAM_OFFSET0 0x40000000 #define SRAM_OFFSET1 0x00200000 #define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) +#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|\ + SRAM_OFFSET2) #define LOW_LEVEL_SRAM_STACK 0x4020FFFC -/* FPGA on Debug board.*/ -#define ETH_CONTROL_REG (DEBUG_BASE+0x30b) -#define LAN_RESET_REGISTER (DEBUG_BASE+0x1c) - -#define DIP_SWITCH_INPUT_REG2 (DEBUG_BASE+0x60) -#define LED_REGISTER (DEBUG_BASE+0x40) -#define FPGA_REV_REGISTER (DEBUG_BASE+0x10) -#define EEPROM_MAIN_BRD (DEBUG_BASE+0x10000+0x1800) -#define EEPROM_CONN_BRD (DEBUG_BASE+0x10000+0x1900) -#define EEPROM_UI_BRD (DEBUG_BASE+0x10000+0x1A00) -#define EEPROM_MCAM_BRD (DEBUG_BASE+0x10000+0x1B00) -#define ENHANCED_UI_EE_NAME "750-2075" +#define DEBUG_LED1 149 /* gpio */ +#define DEBUG_LED2 150 /* gpio */ -#elif (CONFIG_OMAP3_BEAGLE) +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module */ +#define DDR_STACKED 3 /* stacked part on 2422 */ +#define DDR_COMBO 2 /* combo part on cpu daughter card */ +#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00200000 -#define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) +#define CPU_3430 0x3430 -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC +/* 343x real hardware: + * ES1 = rev 0 + */ -#define DEBUG_LED1 149 /* gpio */ -#define DEBUG_LED2 150 /* gpio */ +/* 343x code defines: + * ES1 = 0+1 = 1 + * ES1 = 1+1 = 1 + */ +#define CPU_3430_ES1 1 +#define CPU_3430_ES2 2 + +#define WIDTH_8BIT 0x0000 +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ -#endif /* endif (CONFIG_3430SDP) */ +/* SDP definitions according to FPGA Rev. Is this OK?? */ +#define SDP_3430_V1 0x1 +#define SDP_3430_V2 0x2 #endif Index: uboot-beagle/include/configs/omap3530beagle.h =================================================================== --- uboot-beagle.orig/include/configs/omap3530beagle.h +++ uboot-beagle/include/configs/omap3530beagle.h @@ -1,10 +1,10 @@ /* - * (C) Copyright 2006 + * (C) Copyright 2006-2008 * Texas Instruments. * Richard Woodruff * Syed Mohammed Khasim * - * Configuration settings for the 3430 TI SDP3430 board. + * Configuration settings for the TI OMAP3530 Beagle board. * * See file CREDITS for list of people who contributed to this * project. @@ -27,6 +27,7 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include /* * High Level Configuration Options @@ -39,6 +40,7 @@ #define CONFIG_DOS_PARTITION 1 #include /* get chip and board defs */ +#include /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ @@ -55,9 +57,9 @@ /* * Size of malloc() pool */ -#define CFG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ +#define CFG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ #define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) -#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ /* * Hardware drivers @@ -139,15 +141,16 @@ #define CFG_NAND_WP #define CONFIG_JFFS2_NAND -#define CONFIG_JFFS2_DEV "nand0" /* nand device jffs2 lives on */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 /* start of jffs2 partition */ +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 partition */ /* Environment information */ #define CONFIG_BOOTDELAY 10 -#define CONFIG_BOOTCOMMAND \ - "mmcinit;fatload mmc 0 0x80300000 uImage; fatload mmc 0 0x81600000 rd-ext2.bin; bootm 0x80300000\0" +#define CONFIG_BOOTCOMMAND "mmcinit;fatload mmc 0 0x80300000 uImage; fatload mmc 0 0x81600000 rd-ext2.bin; bootm 0x80300000\0" #define CONFIG_BOOTARGS "setenv bootargs console=ttyS2,115200n8 ramdisk_size=3072 root=/dev/ram0 rw rootfstype=ext2 initrd=0x81600000,3M " @@ -170,11 +173,11 @@ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ -#define CFG_MEMTEST_END (OMAP34XX_SDRC_CS0+SZ_31M) +#define CFG_MEMTEST_END (OMAP34XX_SDRC_CS0+0x01F00000) /* 31MB */ #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ +#define CFG_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ /* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. @@ -270,14 +273,18 @@ extern unsigned int boot_flash_type; #endif -#define WRITE_NAND_COMMAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD)) -#define WRITE_NAND_ADDRESS(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR)) +#define WRITE_NAND_COMMAND(d, adr)\ + __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD)) +#define WRITE_NAND_ADDRESS(d, adr)\ + __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR)) #define WRITE_NAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_DAT)) #define READ_NAND(adr) __raw_readw((nand_cs_base + GPMC_NAND_DAT)) /* Other NAND Access APIs */ -#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) -#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) +#define NAND_WP_OFF()\ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0) +#define NAND_WP_ON()\ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0) #define NAND_DISABLE_CE(nand) #define NAND_ENABLE_CE(nand) #define NAND_WAIT_READY(nand) udelay(10) Index: uboot-beagle/cpu/omap3/start.S =================================================================== --- uboot-beagle.orig/cpu/omap3/start.S +++ uboot-beagle/cpu/omap3/start.S @@ -31,7 +31,6 @@ #include #include -#include .globl _start _start: b reset Index: uboot-beagle/cpu/omap3/interrupts.c =================================================================== --- uboot-beagle.orig/cpu/omap3/interrupts.c +++ uboot-beagle/cpu/omap3/interrupts.c @@ -35,10 +35,6 @@ #include #include -#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) -# include -#endif - #include #define TIMER_LOAD_VAL 0 Index: uboot-beagle/cpu/omap3/cpu.c =================================================================== --- uboot-beagle.orig/cpu/omap3/cpu.c +++ uboot-beagle/cpu/omap3/cpu.c @@ -34,10 +34,6 @@ #include #include #include -#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) -#include -#endif -#include #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; Index: uboot-beagle/board/omap3530beagle/clock.c =================================================================== --- uboot-beagle.orig/board/omap3530beagle/clock.c +++ uboot-beagle/board/omap3530beagle/clock.c @@ -27,14 +27,12 @@ */ #include -#include #include #include #include #include #include #include -#include #include #include Index: uboot-beagle/board/omap3530beagle/lowlevel_init.S =================================================================== --- uboot-beagle.orig/board/omap3530beagle/lowlevel_init.S +++ uboot-beagle/board/omap3530beagle/lowlevel_init.S @@ -29,7 +29,6 @@ #include #include -#include #include #include Index: uboot-beagle/board/omap3530beagle/mem.c =================================================================== --- uboot-beagle.orig/board/omap3530beagle/mem.c +++ uboot-beagle/board/omap3530beagle/mem.c @@ -23,7 +23,6 @@ */ #include -#include #include #include #include Index: uboot-beagle/board/omap3530beagle/nand.c =================================================================== --- uboot-beagle.orig/board/omap3530beagle/nand.c +++ uboot-beagle/board/omap3530beagle/nand.c @@ -23,7 +23,6 @@ #include #include -#include #include #include Index: uboot-beagle/board/omap3530beagle/omap3530beagle.c =================================================================== --- uboot-beagle.orig/board/omap3530beagle/omap3530beagle.c +++ uboot-beagle/board/omap3530beagle/omap3530beagle.c @@ -30,12 +30,10 @@ * MA 02111-1307 USA */ #include -#include #include #include #include #include -#include #include #include #include Index: uboot-beagle/board/omap3530beagle/sys_info.c =================================================================== --- uboot-beagle.orig/board/omap3530beagle/sys_info.c +++ uboot-beagle/board/omap3530beagle/sys_info.c @@ -23,12 +23,10 @@ */ #include -#include #include #include #include /* get mem tables */ #include -#include #include /************************************************************************** Index: uboot-beagle/board/omap3530beagle/syslib.c =================================================================== --- uboot-beagle.orig/board/omap3530beagle/syslib.c +++ uboot-beagle/board/omap3530beagle/syslib.c @@ -22,13 +22,11 @@ */ #include -#include #include #include #include #include #include -#include /************************************************************ * sdelay() - simple spin loop. Will be constant time as Index: uboot-beagle/include/asm-arm/arch-omap3/sizes.h =================================================================== --- uboot-beagle.orig/include/asm-arm/arch-omap3/sizes.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_31M 0x01F00000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __sizes_h */ Index: uboot-beagle/include/asm-arm/arch-omap3/i2c.h =================================================================== --- uboot-beagle.orig/include/asm-arm/arch-omap3/i2c.h +++ uboot-beagle/include/asm-arm/arch-omap3/i2c.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004-2006 + * (C) Copyright 2004-2008 * Texas Instruments, * * See file CREDITS for list of people who contributed to this @@ -20,11 +20,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef _OMAP34XX_I2C_H_ -#define _OMAP34XX_I2C_H_ - -/* Get the i2c base addresses */ -#include +#ifndef _I2C_H_ +#define _I2C_H_ #define I2C_DEFAULT_BASE I2C_BASE1 @@ -48,25 +45,25 @@ /* I2C Interrupt Enable Register (I2C_IE): */ #define I2C_IE_GC_IE (1 << 5) -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ /* I2C Status Register (I2C_STAT): */ -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_SBD (1 << 15) /* Single byte data */ +#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ #define I2C_STAT_GC (1 << 5) -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ /* I2C Interrupt Code Register (I2C_INTCODE): */ @@ -80,30 +77,31 @@ /* I2C Buffer Configuration Register (I2C_BUF): */ -#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ -#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ +#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ +#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ /* I2C Configuration Register (I2C_CON): */ -#define I2C_CON_EN (1 << 15) /* I2C module enable */ -#define I2C_CON_BE (1 << 14) /* Big endian mode */ -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ +#define I2C_CON_EN (1 << 15) /* I2C module enable */ +#define I2C_CON_BE (1 << 14) /* Big endian mode */ +#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode /* + /* (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ /* I2C System Test Register (I2C_SYSTEST): */ -#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ -#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ -#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ -#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ -#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ -#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ -#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ +#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ +#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */ +#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ +#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ +#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ +#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ +#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ +#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ #define I2C_SCLL_SCLL (0) #define I2C_SCLL_SCLL_M (0xFF) @@ -114,17 +112,17 @@ #define I2C_SCLH_HSSCLH (8) #define I2C_SCLH_HSSCLH_M (0xFF) -#define OMAP_I2C_STANDARD 100 -#define OMAP_I2C_FAST_MODE 400 -#define OMAP_I2C_HIGH_SPEED 3400 - -#define SYSTEM_CLOCK_12 12000 -#define SYSTEM_CLOCK_13 13000 -#define SYSTEM_CLOCK_192 19200 -#define SYSTEM_CLOCK_96 96000 +#define OMAP_I2C_STANDARD 100 +#define OMAP_I2C_FAST_MODE 400 +#define OMAP_I2C_HIGH_SPEED 3400 + +#define SYSTEM_CLOCK_12 12000 +#define SYSTEM_CLOCK_13 13000 +#define SYSTEM_CLOCK_192 19200 +#define SYSTEM_CLOCK_96 96000 #define I2C_IP_CLK SYSTEM_CLOCK_96 #define I2C_PSC_MAX (0x0f) #define I2C_PSC_MIN (0x00) -#endif +#endif /* _I2C_H_ */ Index: uboot-beagle/include/asm-arm/arch-omap3/mem.h =================================================================== --- uboot-beagle.orig/include/asm-arm/arch-omap3/mem.h +++ uboot-beagle/include/asm-arm/arch-omap3/mem.h @@ -26,7 +26,7 @@ #define _MEM_H_ #define SDRC_CS0_OSET 0x0 -#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ +#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ #ifndef __ASSEMBLY__ @@ -46,7 +46,7 @@ typedef enum { #define SDP_SDRC_MR_0_SDR 0x00000031 /* optimized timings good for current shipping parts */ -#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ +#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ #define DLL_OFFSET 0 #define DLL_WRITEDDRCLKX2DIS 1 @@ -55,7 +55,7 @@ typedef enum { #define DLL_DLLPHASE_72 0 #define DLL_DLLPHASE_90 1 -// rkw - need to find of 90/72 degree recommendation for speed like before. +/* rkw - need to find of 90/72 degree recommendation for speed like before */ #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) @@ -82,15 +82,15 @@ typedef enum { #define TRC_165 10 #define TRFC_165 12 #define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | (TRAS_165 << 18) \ - | (TRP_165 << 15) | (TRCD_165 << 12) |(TRRD_165 << 9) | \ + | (TRP_165 << 15) | (TRCD_165 << 12) | (TRRD_165 << 9) | \ (TDPL_165 << 6) | (TDAL_165)) #define TWTR_165 1 #define TCKE_165 2 #define TXP_165 2 #define XSR_165 20 -#define V_ACTIMB_165 ((TCKE_165 << 12) | (XSR_165 << 0)) | \ - (TXP_165 << 8) | (TWTR_165 << 16) +#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \ + (TXP_165 << 8) | (TWTR_165 << 16)) # define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 # define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165 @@ -105,9 +105,9 @@ typedef enum { * x is GPMC config registers from 1 to 6 (there will be 6 macros) * Value is corresponding value * - * For every valid PRCM configuration there should be only one definition of - * the same. if values are independent of the board, this definition will be - * present in this file if values are dependent on the board, then this should + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should * go into corresponding mem-boardName.h file * * Currently valid part Names are (PART): Index: uboot-beagle/include/asm-arm/arch-omap3/sys_info.h =================================================================== --- uboot-beagle.orig/include/asm-arm/arch-omap3/sys_info.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP34XX_SYS_INFO_H_ -#define _OMAP34XX_SYS_INFO_H_ - -#define XDR_POP 5 /* package on package part */ -#define SDR_DISCRETE 4 /* 128M memory SDR module */ -#define DDR_STACKED 3 /* stacked part on 2422 */ -#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ -#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_3430 0x3430 - -/* 343x real hardware: - * ES1 = rev 0 - */ - -/* 343x code defines: - * ES1 = 0+1 = 1 - * ES1 = 1+1 = 1 - */ -#define CPU_3430_ES1 1 -#define CPU_3430_ES2 2 - -/* Currently Virtio models this one */ -#define CPU_3430_CHIPID 0x0B68A000 - -#define GPMC_MUXED 1 -#define GPMC_NONMUXED 0 - -#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ -#define TYPE_NOR 0x000 -#define TYPE_ONENAND 0x800 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ -#define I2C_TRITON2 0x4B /* addres of power group */ - -#define BOOT_FAST_XIP 0x1f - -/* SDP definitions according to FPGA Rev. Is this OK?? */ -#define SDP_3430_V1 0x1 -#define SDP_3430_V2 0x2 - -#endif