Subject: ARM: OMAP3: Switch from march=armv7a to armv5 From: Dirk Behme In upstream preparation, switch from march=armv7a to armv5. This will allow upstream to use more compilers and we don't have to change top level Makefile for OMAP3. When patches go upstream, we won't change CROSS_COMPILE = arm-linux- . To use CodeSourcery tool chain, this can be overwritten at command line using CROSS_COMPILE = arm-none-linux-gnueabi- then. With armv5, resulting u-boot.bin is only ~500 bytes larger than with armv7a. Signed-off-by: Dirk Behme --- cpu/omap3/config.mk | 6 ++++-- cpu/omap3/start.S | 11 ++++++++--- 2 files changed, 12 insertions(+), 5 deletions(-) Index: u-boot_steve/cpu/omap3/config.mk =================================================================== --- u-boot_steve.orig/cpu/omap3/config.mk +++ u-boot_steve/cpu/omap3/config.mk @@ -21,14 +21,16 @@ # MA 02111-1307 USA # PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float + -msoft-float -PLATFORM_CPPFLAGS += -march=armv7a +# Make ARMv5 to allow more compilers to work, even though its v7a. +PLATFORM_CPPFLAGS += -march=armv5 # ========================================================================= # # Supply options according to compiler version # # ========================================================================= PLATFORM_CPPFLAGS +=$(call cc-option) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\ $(call cc-option,-malignment-traps,)) Index: u-boot_steve/cpu/omap3/start.S =================================================================== --- u-boot_steve.orig/cpu/omap3/start.S +++ u-boot_steve/cpu/omap3/start.S @@ -463,8 +463,11 @@ inval_loop1: @ i-cache mcr p15, 2, r10, c0, c0, 0 @ select current cache level @ in cssr - isb @ isb to sych the new - @ cssr&csidr + mov r2, #0 @ operand for mcr SBZ + mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to + @ sych the new cssr&csidr, + @ with armv7 this is 'isb', + @ but we compile with armv5 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr and r2, r1, #7 @ extract the length of the @ cache lines @@ -497,7 +500,9 @@ finished_inval: mov r10, #0 @ swith back to cache level 0 mcr p15, 2, r10, c0, c0, 0 @ select current cache level @ in cssr - isb + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, + @ with armv7 this is 'isb', + @ but we compile with armv5 ldmfd r13!, {r0-r5, r7, r9-r12,pc}