From: Dirk Behme Clean up start code Signed-off-by: Dirk Behme -- Index: uboot_beagle/cpu/omap3/start.S =================================================================== --- uboot_beagle.orig/cpu/omap3/start.S +++ uboot_beagle/cpu/omap3/start.S @@ -1,5 +1,5 @@ /* - * armboot - Startup Code for OMAP3430/ARM Cortex CPU-core + * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core * * Copyright (c) 2004 Texas Instruments * @@ -8,7 +8,7 @@ * Copyright (c) 2002 Gary Jennejohn * Copyright (c) 2003 Richard Woodruff * Copyright (c) 2003 Kshitij - * Copyright (c) 2006 Syed Mohammed Khasim + * Copyright (c) 2006-2008 Syed Mohammed Khasim * * See file CREDITS for list of people who contributed to this * project. @@ -31,9 +31,8 @@ #include #include -#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) #include -#endif + .globl _start _start: b reset ldr pc, _undefined_instruction @@ -56,8 +55,7 @@ _pad: .word 0x12345678 /* now 16*4=64 _end_vect: .balignl 16,0xdeadbeef -/* - ************************************************************************* +/************************************************************************* * * Startup Code (reset vector) * @@ -66,8 +64,7 @@ _end_vect: * relocate armboot to ram * setup stack * - ************************************************************************* - */ + *************************************************************************/ _TEXT_BASE: .word TEXT_BASE @@ -114,95 +111,93 @@ reset: #if (CONFIG_OMAP34XX) /* Copy vectors to mask ROM indirect addr */ - adr r0, _start /* r0 <- current position of code */ - add r0, r0, #4 /* skip reset vector */ - mov r2, #64 /* r2 <- size to copy */ - add r2, r0, r2 /* r2 <- source end address */ - mov r1, #SRAM_OFFSET0 /* build vect addr */ + adr r0, _start @ r0 <- current position of code + add r0, r0, #4 @ skip reset vector + mov r2, #64 @ r2 <- size to copy + add r2, r0, r2 @ r2 <- source end address + mov r1, #SRAM_OFFSET0 @ build vect addr mov r3, #SRAM_OFFSET1 add r1, r1, r3 mov r3, #SRAM_OFFSET2 add r1, r1, r3 next: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next /* loop until equal */ + ldmia r0!, {r3-r10} @ copy from source address [r0] + stmia r1!, {r3-r10} @ copy to target address [r1] + cmp r0, r2 @ until source end address [r2] + bne next @ loop until equal */ #if !defined(CFG_NAND_BOOT) && !defined(CFG_ONENAND_BOOT) /* No need to copy/exec the clock code - DPLL adjust already done * in NAND/oneNAND Boot. */ - bl cpy_clk_code /* put dpll adjust code behind vectors */ + bl cpy_clk_code @ put dpll adjust code behind vectors #endif /* NAND Boot */ -#endif /* 24xx */ +#endif /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit #endif #ifndef CONFIG_SKIP_RELOCATE_UBOOT -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ +relocate: @ relocate U-Boot to RAM + adr r0, _start @ r0 <- current position of code + ldr r1, _TEXT_BASE @ test if we run from flash or RAM + cmp r0, r1 @ don't reloc during debug beq stack_setup ldr r2, _armboot_start ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ + sub r2, r3, r2 @ r2 <- size of armboot + add r2, r0, r2 @ r2 <- source end address -copy_loop: /* copy 32 bytes at a time */ - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ +copy_loop: @ copy 32 bytes at a time + ldmia r0!, {r3-r10} @ copy from source address [r0] + stmia r1!, {r3-r10} @ copy to target address [r1] + cmp r0, r2 @ until source end addreee [r2] ble copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ - /* Set up the stack */ + /* Set up the stack */ stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot + sub r0, r0, #CFG_MALLOC_LEN @ malloc area + sub r0, r0, #CFG_GBL_DATA_SIZE @ bdinfo #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif - sub sp, r0, #12 /* leave 3 words for abort-stack */ - and sp, sp, #~7 /* 8 byte alinged for (ldr/str)d */ + sub sp, r0, #12 @ leave 3 words for abort-stack + and sp, sp, #~7 @ 8 byte alinged for (ldr/str)d /* Clear BSS (if any). Is below tx (watch load addr - need space) */ clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear value */ + ldr r0, _bss_start @ find start of bss segment + ldr r1, _bss_end @ stop here + mov r2, #0x00000000 @ clear value clbss_l: - str r2, [r0] /* clear BSS location */ - cmp r0, r1 /* are we at the end yet */ - add r0, r0, #4 /* increment clear index pointer */ - bne clbss_l /* keep clearing till at end */ + str r2, [r0] @ clear BSS location + cmp r0, r1 @ are we at the end yet + add r0, r0, #4 @ increment clear index pointer + bne clbss_l @ keep clearing till at end - ldr pc, _start_armboot /* jump to C code */ + ldr pc, _start_armboot @ jump to C code _start_armboot: .word start_armboot -/* - ************************************************************************* +/************************************************************************* * * CPU_init_critical registers * * setup important registers * setup memory timing * - ************************************************************************* - */ + *************************************************************************/ cpu_init_crit: /* * Invalidate L1 I/D */ - mov r0, #0 /* set up for MCR */ - mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ - mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ + mov r0, #0 @ set up for MCR + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs + mcr p15, 0, r0, c7, c5, 0 @ invalidate icache /* * disable MMU stuff and caches @@ -215,13 +210,15 @@ cpu_init_crit: mcr p15, 0, r0, c1, c0, 0 /* - * Jump to board specific initialization... The Mask ROM will have already initialized - * basic memory. Go here to bump up clock rate and handle wake up conditions. + * Jump to board specific initialization... + * The Mask ROM will have already initialized + * basic memory. Go here to bump up clock rate and handle + * wake up conditions. */ - mov ip, lr /* persevere link reg across call */ - bl lowlevel_init /* go setup pll,mux,memory */ - mov lr, ip /* restore link */ - mov pc, lr /* back to my caller */ + mov ip, lr @ persevere link reg across call + bl lowlevel_init @ go setup pll,mux,memory + mov lr, ip @ restore link + mov pc, lr @ back to my caller /* ************************************************************************* * @@ -263,25 +260,32 @@ cpu_init_crit: */ .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 + sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current + @ user stack + stmia sp, {r0 - r12} @ Save user registers (now in + @ svc mode) r0-r12 ldr r2, _armboot_start sub r2, r2, #(CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack - ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort + @ stack + ldmia r2, {r2 - r3} @ get values for "aborted" pc + @ and cpsr (into parm regs) add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack add r5, sp, #S_SP mov r1, lr stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) + mov r0, sp @ save current stack into r0 + @ (param register) .endm .macro irq_save_user_regs sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. + add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! + @ a reserved stack spot would + @ be good. stmdb r8, {sp, lr}^ @ Calling SP, LR str lr, [r8, #0] @ Save calling PC mrs r6, spsr @@ -295,34 +299,45 @@ cpu_init_crit: mov r0, r0 ldr lr, [sp, #S_PC] @ Get PC add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr + subs pc, lr, #4 @ return & move spsr_svc into + @ cpsr .endm .macro get_bad_stack - ldr r13, _armboot_start @ setup our mode stack (enter in banked mode) + ldr r13, _armboot_start @ setup our mode stack (enter + @ in banked mode) sub r13, r13, #(CFG_MALLOC_LEN) @ move past malloc pool - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ move to reserved a couple + @ spots for abort stack - str lr, [r13] @ save caller lr in position 0 of saved stack + str lr, [r13] @ save caller lr in position 0 + @ of saved stack mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack + str lr, [r13, #4] @ save spsr in position 1 of + @ saved stack mov r13, #MODE_SVC @ prepare SVC-Mode @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute + msr spsr, r13 @ switch modes, make sure + @ moves will execute mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. + movs pc, lr @ jump to next instruction & + @ switch modes. .endm .macro get_bad_stack_swi - sub r13, r13, #4 @ space on current stack for scratch reg. + sub r13, r13, #4 @ space on current stack for + @ scratch reg. str r0, [r13] @ save R0's value. ldr r0, _armboot_start @ get data regions start sub r0, r0, #(CFG_MALLOC_LEN) @ move past malloc pool - sub r0, r0, #(CFG_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack - str lr, [r0] @ save caller lr in position 0 of saved stack + sub r0, r0, #(CFG_GBL_DATA_SIZE+8) @ move past gbl and a couple + @ spots for abort stack + str lr, [r0] @ save caller lr in position 0 + @ of saved stack mrs r0, spsr @ get the spsr - str lr, [r0, #4] @ save spsr in position 1 of saved stack + str lr, [r0, #4] @ save spsr in position 1 of + @ saved stack ldr r0, [r13] @ restore r0 add r13, r13, #4 @ pop stack entry .endm @@ -403,8 +418,8 @@ fiq: .align 5 .global arm_cache_flush arm_cache_flush: - mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache - mov pc, lr @ back to caller + mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache + mov pc, lr @ back to caller /* * v7_flush_dcache_all() @@ -421,37 +436,54 @@ v7_flush_dcache_all: stmfd r13!, {r0-r5, r7, r9-r12,r14} mov r7, r0 @ take a backup of device type - cmp r0, #0x3 @ check if the device type is GP - moveq r12, #0x1 @ set up to invalide L2 + cmp r0, #0x3 @ check if the device type is + @ GP + moveq r12, #0x1 @ set up to invalide L2 smi: .word 0x01600070 @ Call SMI monitor (smieq) - cmp r7, #0x3 @ compare again in case its lost - beq finished_inval @ if GP device, inval done above + cmp r7, #0x3 @ compare again in case its + @ lost + beq finished_inval @ if GP device, inval done + @ above mrc p15, 1, r0, c0, c0, 1 @ read clidr ands r3, r0, #0x7000000 @ extract loc from clidr mov r3, r3, lsr #23 @ left align loc bit field - beq finished_inval @ if loc is 0, then no need to clean + beq finished_inval @ if loc is 0, then no need to + @ clean mov r10, #0 @ start clean at cache level 0 inval_loop1: - add r2, r10, r10, lsr #1 @ work out 3x current cache level - mov r1, r0, lsr r2 @ extract cache type bits from clidr - and r1, r1, #7 @ mask of the bits for current cache only - cmp r1, #2 @ see what cache we have at this level - blt skip_inval @ skip if no cache, or just i-cache - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr - isb @ isb to sych the new cssr&csidr + add r2, r10, r10, lsr #1 @ work out 3x current cache + @ level + mov r1, r0, lsr r2 @ extract cache type bits from + @ clidr + and r1, r1, #7 @ mask of the bits for current + @ cache only + cmp r1, #2 @ see what cache we have at + @ this level + blt skip_inval @ skip if no cache, or just + @ i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + isb @ isb to sych the new + @ cssr&csidr mrc p15, 1, r1, c0, c0, 0 @ read the new csidr - and r2, r1, #7 @ extract the length of the cache lines + and r2, r1, #7 @ extract the length of the + @ cache lines add r2, r2, #4 @ add 4 (line length offset) ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 @ find maximum number on the way size - clz r5, r4 @ find bit position of way size increment + ands r4, r4, r1, lsr #3 @ find maximum number on the + @ way size + clz r5, r4 @ find bit position of way + @ size increment ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 @ extract max number of the index size + ands r7, r7, r1, lsr #13 @ extract max number of the + @ index size inval_loop2: - mov r9, r4 @ create working copy of max way size + mov r9, r4 @ create working copy of max + @ way size inval_loop3: - orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 + orr r11, r10, r9, lsl r5 @ factor way and cache number + @ into r11 orr r11, r11, r7, lsl r2 @ factor index number into r11 mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way subs r9, r9, #1 @ decrement the way @@ -464,18 +496,20 @@ skip_inval: bgt inval_loop1 finished_inval: mov r10, #0 @ swith back to cache level 0 - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr isb - + ldmfd r13!, {r0-r5, r7, r9-r12,pc} - + .align 5 .global reset_cpu reset_cpu: - ldr r1, rstctl /* get addr for global reset reg */ - mov r3, #0x2 /* full reset pll+mpu */ - str r3, [r1] /* force reset */ + ldr r1, rstctl @ get addr for global reset + @ reg + mov r3, #0x2 @ full reset pll + mpu + str r3, [r1] @ force reset mov r0, r0 _loop_forever: b _loop_forever