Add I2C multibus support for OMAP2/3 boards

Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>
---

diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index 16439ac..ed4384f 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -1370,6 +1370,14 @@ U_BOOT_CMD(
 	"    - loop, reading a set of addresses\n"
 );
 
+#if defined(CONFIG_I2C_MULTI_BUS)
+U_BOOT_CMD(
+	ide,	2,	1,	do_i2c_bus_num,
+	"ide	- i2c bus select\n",          
+	"bus\n	- i2c bus select\n"
+);
+#endif
+
 #if defined(CONFIG_CMD_SDRAM)
 U_BOOT_CMD(
 	isdram,	2,	1,	do_sdram,

diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 6784603..3976602 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -25,40 +25,53 @@
 #include <asm/arch/i2c.h>
 #include <asm/io.h>
 
+#ifdef CONFIG_OMAP34XX
+#define I2C_NUM_IF 3
+#else
+#define I2C_NUM_IF 2
+#endif
+
 static void wait_for_bb (void);
 static u16 wait_for_pin (void);
 static void flush_fifo(void);
 
+static u32 i2c_base = I2C_DEFAULT_BASE;
+
+#define i2c_readb(a)			readb(i2c_base + (a))
+#define i2c_writeb(v,a)		writeb((v), (i2c_base + (a)))
+#define i2c_readw(a)			readw(i2c_base +(a))
+#define i2c_writew(v,a)		writew((v), (i2c_base + (a)))
+
 void i2c_init (int speed, int slaveadd)
 {
 	u16 scl;
 
-	writew(0x2, I2C_SYSC); /* for ES2 after soft reset */
+	i2c_writew(0x2, I2C_SYSC); /* for ES2 after soft reset */
 	udelay(1000);
-	writew(0x0, I2C_SYSC); /* will probably self clear but */
+	i2c_writew(0x0, I2C_SYSC); /* will probably self clear but */
 
-	if (readw (I2C_CON) & I2C_CON_EN) {
-		writew (0, I2C_CON);
+	if (i2c_readw (I2C_CON) & I2C_CON_EN) {
+		i2c_writew (0, I2C_CON);
 		udelay (50000);
 	}
 
 	/* 12MHz I2C module clock */
-	writew (0, I2C_PSC);
+	i2c_writew (0, I2C_PSC);
 	speed = speed/1000;		    /* 100 or 400 */
 	scl = ((12000/(speed*2)) - 7);	/* use 7 when PSC = 0 */
-	writew (scl, I2C_SCLL);
-	writew (scl, I2C_SCLH);
+	i2c_writew (scl, I2C_SCLL);
+	i2c_writew (scl, I2C_SCLH);
 	/* own address */
-	writew (slaveadd, I2C_OA);
-	writew (I2C_CON_EN, I2C_CON);
+	i2c_writew (slaveadd, I2C_OA);
+	i2c_writew (I2C_CON_EN, I2C_CON);
 
 	/* have to enable intrrupts or OMAP i2c module doesn't work */
-	writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
+	i2c_writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
 		I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE);
 	udelay (1000);
 	flush_fifo();
-	writew (0xFFFF, I2C_STAT);
-	writew (0, I2C_CNT);
+	i2c_writew (0xFFFF, I2C_STAT);
+	i2c_writew (0, I2C_CNT);
 }
 
 static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
@@ -70,19 +83,19 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
 	wait_for_bb ();
 
 	/* one byte only */
-	writew (1, I2C_CNT);
+	i2c_writew (1, I2C_CNT);
 	/* set slave address */
-	writew (devaddr, I2C_SA);
+	i2c_writew (devaddr, I2C_SA);
 	/* no stop bit needed here */
-	writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON);
+	i2c_writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON);
 
 	status = wait_for_pin ();
 
 	if (status & I2C_STAT_XRDY) {
 		/* Important: have to use byte access */
-		writeb (regoffset, I2C_DATA);
+		i2c_writeb (regoffset, I2C_DATA);
 		udelay (20000);
-		if (readw (I2C_STAT) & I2C_STAT_NACK) {
+		if (i2c_readw (I2C_STAT) & I2C_STAT_NACK) {
 			i2c_error = 1;
 		}
 	} else {
@@ -91,28 +104,28 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
 
 	if (!i2c_error) {
 		/* free bus, otherwise we can't use a combined transction */
-		writew (0, I2C_CON);
-		while (readw (I2C_STAT) || (readw (I2C_CON) & I2C_CON_MST)) {
+		i2c_writew (0, I2C_CON);
+		while (i2c_readw (I2C_STAT) || (i2c_readw (I2C_CON) & I2C_CON_MST)) {
 			udelay (10000);
 			/* Have to clear pending interrupt to clear I2C_STAT */
-			writew (0xFFFF, I2C_STAT);
+			i2c_writew (0xFFFF, I2C_STAT);
 		}
 
 		wait_for_bb ();
 		/* set slave address */
-		writew (devaddr, I2C_SA);
+		i2c_writew (devaddr, I2C_SA);
 		/* read one byte from slave */
-		writew (1, I2C_CNT);
+		i2c_writew (1, I2C_CNT);
 		/* need stop bit here */
-		writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
+		i2c_writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
 			I2C_CON);
 
 		status = wait_for_pin ();
 		if (status & I2C_STAT_RRDY) {
 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
-			*value = readb (I2C_DATA);
+			*value = i2c_readb (I2C_DATA);
 #else
-			*value = readw (I2C_DATA);
+			*value = i2c_readw (I2C_DATA);
 #endif
 			udelay (20000);
 		} else {
@@ -120,17 +133,17 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
 		}
 
 		if (!i2c_error) {
-			writew (I2C_CON_EN, I2C_CON);
-			while (readw (I2C_STAT)
-			       || (readw (I2C_CON) & I2C_CON_MST)) {
+			i2c_writew (I2C_CON_EN, I2C_CON);
+			while (i2c_readw (I2C_STAT)
+			       || (i2c_readw (I2C_CON) & I2C_CON_MST)) {
 				udelay (10000);
-				writew (0xFFFF, I2C_STAT);
+				i2c_writew (0xFFFF, I2C_STAT);
 			}
 		}
 	}
 	flush_fifo();
-	writew (0xFFFF, I2C_STAT);
-	writew (0, I2C_CNT);
+	i2c_writew (0xFFFF, I2C_STAT);
+	i2c_writew (0, I2C_CNT);
 	return i2c_error;
 }
 
@@ -143,11 +156,11 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
 	wait_for_bb ();
 
 	/* two bytes */
-	writew (2, I2C_CNT);
+	i2c_writew (2, I2C_CNT);
 	/* set slave address */
-	writew (devaddr, I2C_SA);
+	i2c_writew (devaddr, I2C_SA);
 	/* stop bit needed here */
-	writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
+	i2c_writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
 		I2C_CON_STP, I2C_CON);
 
 	/* wait until state change */
@@ -156,24 +169,24 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
 	if (status & I2C_STAT_XRDY) {
 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
 		/* send out 1 byte */
-		writeb (regoffset, I2C_DATA);
-		writew (I2C_STAT_XRDY, I2C_STAT);
+		i2c_writeb (regoffset, I2C_DATA);
+		i2c_writew (I2C_STAT_XRDY, I2C_STAT);
 
 		status = wait_for_pin ();
 		if ((status & I2C_STAT_XRDY)) {
 			/* send out next 1 byte */
-			writeb (value, I2C_DATA);
-			writew (I2C_STAT_XRDY, I2C_STAT);
+			i2c_writeb (value, I2C_DATA);
+			i2c_writew (I2C_STAT_XRDY, I2C_STAT);
 		} else {
 			i2c_error = 1;
 		}
 #else
 		/* send out two bytes */
-		writew ((value << 8) + regoffset, I2C_DATA);
+		i2c_writew ((value << 8) + regoffset, I2C_DATA);
 #endif
 		/* must have enough delay to allow BB bit to go low */
 		udelay (50000);
-		if (readw (I2C_STAT) & I2C_STAT_NACK) {
+		if (i2c_readw (I2C_STAT) & I2C_STAT_NACK) {
 			i2c_error = 1;
 		}
 	} else {
@@ -183,18 +196,18 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
 	if (!i2c_error) {
 		int eout = 200;
 
-		writew (I2C_CON_EN, I2C_CON);
-		while ((stat = readw (I2C_STAT)) || (readw (I2C_CON) & I2C_CON_MST)) {
+		i2c_writew (I2C_CON_EN, I2C_CON);
+		while ((stat = i2c_readw (I2C_STAT)) || (i2c_readw (I2C_CON) & I2C_CON_MST)) {
 			udelay (1000);
 			/* have to read to clear intrrupt */
-			writew (0xFFFF, I2C_STAT);
+			i2c_writew (0xFFFF, I2C_STAT);
 			if(--eout == 0) /* better leave with error than hang */
 				break;
 		}
 	}
 	flush_fifo();
-	writew (0xFFFF, I2C_STAT);
-	writew (0, I2C_CNT);
+	i2c_writew (0xFFFF, I2C_STAT);
+	i2c_writew (0, I2C_CNT);
 	return i2c_error;
 }
 
@@ -205,14 +218,14 @@ static void flush_fifo(void)
 	 * you get a bus error
 	 */
 	while(1){
-		stat = readw(I2C_STAT);
+		stat = i2c_readw(I2C_STAT);
 		if(stat == I2C_STAT_RRDY){
 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
-			readb(I2C_DATA);
+			i2c_readb(I2C_DATA);
 #else
-			readw(I2C_DATA);
+			i2c_readw(I2C_DATA);
 #endif
-			writew(I2C_STAT_RRDY,I2C_STAT);
+			i2c_writew(I2C_STAT_RRDY,I2C_STAT);
 			udelay(1000);
 		}else
 			break;
@@ -223,7 +236,7 @@ int i2c_probe (uchar chip)
 {
 	int res = 1; /* default = fail */
 
-	if (chip == readw (I2C_OA)) {
+	if (chip == i2c_readw (I2C_OA)) {
 		return res;
 	}
 
@@ -231,27 +244,27 @@ int i2c_probe (uchar chip)
 	wait_for_bb ();
 
 	/* try to read one byte */
-	writew (1, I2C_CNT);
+	i2c_writew (1, I2C_CNT);
 	/* set slave address */
-	writew (chip, I2C_SA);
+	i2c_writew (chip, I2C_SA);
 	/* stop bit needed here */
-	writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON);
+	i2c_writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON);
 	/* enough delay for the NACK bit set */
 	udelay (50000);
 
-	if (!(readw (I2C_STAT) & I2C_STAT_NACK)) {
+	if (!(i2c_readw (I2C_STAT) & I2C_STAT_NACK)) {
 		res = 0;      /* success case */
 		flush_fifo();
-		writew(0xFFFF, I2C_STAT);
+		i2c_writew(0xFFFF, I2C_STAT);
 	} else {
-		writew(0xFFFF, I2C_STAT);	 /* failue, clear sources*/
-		writew (readw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */
+		i2c_writew(0xFFFF, I2C_STAT);	 /* failue, clear sources*/
+		i2c_writew (i2c_readw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */
 		udelay(20000);
 		wait_for_bb ();
 	}
 	flush_fifo();
-	writew (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/
-	writew(0xFFFF, I2C_STAT);
+	i2c_writew (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/
+	i2c_writew(0xFFFF, I2C_STAT);
 	return res;
 }
 
@@ -310,17 +323,17 @@ static void wait_for_bb (void)
 	int timeout = 10;
 	u16 stat;
 
-	writew(0xFFFF, I2C_STAT);	 /* clear current interruts...*/
-	while ((stat = readw (I2C_STAT) & I2C_STAT_BB) && timeout--) {
-		writew (stat, I2C_STAT);
+	i2c_writew(0xFFFF, I2C_STAT);	 /* clear current interruts...*/
+	while ((stat = i2c_readw (I2C_STAT) & I2C_STAT_BB) && timeout--) {
+		i2c_writew (stat, I2C_STAT);
 		udelay (50000);
 	}
 
 	if (timeout <= 0) {
 		printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
-			readw (I2C_STAT));
+			i2c_readw (I2C_STAT));
 	}
-	writew(0xFFFF, I2C_STAT);	 /* clear delayed stuff*/
+	i2c_writew(0xFFFF, I2C_STAT);	 /* clear delayed stuff*/
 }
 
 static u16 wait_for_pin (void)
@@ -330,7 +343,7 @@ static u16 wait_for_pin (void)
 
 	do {
 		udelay (1000);
-		status = readw (I2C_STAT);
+		status = i2c_readw (I2C_STAT);
 	} while (  !(status &
 		   (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
 		    I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
@@ -338,8 +351,56 @@ static u16 wait_for_pin (void)
 
 	if (timeout <= 0) {
 		printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
-			readw (I2C_STAT));
-			writew(0xFFFF, I2C_STAT);
+			i2c_readw (I2C_STAT));
+			i2c_writew(0xFFFF, I2C_STAT);
 }
 	return status;
 }
+
+int i2c_set_bus_num(unsigned int bus)
+{
+	if ((bus < 0) || (bus >= I2C_NUM_IF)) {
+		printf("Bad bus ID-%d\n", bus);
+		return -1;
+	}
+	
+#if defined(CONFIG_OMAP34XX)
+	if (bus == 2)
+		i2c_base = I2C_BASE3;
+	else
+#endif
+
+	if (bus == 1)
+		i2c_base = I2C_BASE2;
+	else
+		i2c_base = I2C_BASE1;
+		
+	return 0;       
+}
+
+unsigned int i2c_get_bus_num(void)
+{
+	if (i2c_base == I2C_BASE1)
+		return 0;
+	else
+	if (i2c_base == I2C_BASE2)
+		return 1;
+#if defined(CONFIG_OMAP34XX)
+	else
+		return 3;
+#endif
+}
+
+/*
+ * To be Implemented
+ */
+int i2c_set_bus_speed(unsigned int speed)
+{
+
+}
+
+unsigned int i2c_get_bus_speed()
+{
+
+}
+

diff --git a/include/asm-arm/arch-omap3/i2c.h b/include/asm-arm/arch-omap3/i2c.h
index 3937f35..6a4ee37 100644
--- a/include/asm-arm/arch-omap3/i2c.h
+++ b/include/asm-arm/arch-omap3/i2c.h
@@ -25,21 +25,21 @@
 
 #define I2C_DEFAULT_BASE	I2C_BASE1
 
-#define I2C_REV		(I2C_DEFAULT_BASE + 0x00)
-#define I2C_IE 		(I2C_DEFAULT_BASE + 0x04)
-#define I2C_STAT	(I2C_DEFAULT_BASE + 0x08)
-#define I2C_IV 		(I2C_DEFAULT_BASE + 0x0c)
-#define I2C_BUF		(I2C_DEFAULT_BASE + 0x14)
-#define I2C_CNT		(I2C_DEFAULT_BASE + 0x18)
-#define I2C_DATA	(I2C_DEFAULT_BASE + 0x1c)
-#define I2C_SYSC	(I2C_DEFAULT_BASE + 0x20)
-#define I2C_CON		(I2C_DEFAULT_BASE + 0x24)
-#define I2C_OA 		(I2C_DEFAULT_BASE + 0x28)
-#define I2C_SA 		(I2C_DEFAULT_BASE + 0x2c)
-#define I2C_PSC		(I2C_DEFAULT_BASE + 0x30)
-#define I2C_SCLL	(I2C_DEFAULT_BASE + 0x34)
-#define I2C_SCLH	(I2C_DEFAULT_BASE + 0x38)
-#define I2C_SYSTEST	(I2C_DEFAULT_BASE + 0x3c)
+#define I2C_REV		(0x00)
+#define I2C_IE 		(0x04)
+#define I2C_STAT	(0x08)
+#define I2C_IV 		(0x0c)
+#define I2C_BUF		(0x14)
+#define I2C_CNT		(0x18)
+#define I2C_DATA	(0x1c)
+#define I2C_SYSC	(0x20)
+#define I2C_CON		(0x24)
+#define I2C_OA 		(0x28)
+#define I2C_SA 		(0x2c)
+#define I2C_PSC		(0x30)
+#define I2C_SCLL	(0x34)
+#define I2C_SCLH	(0x38)
+#define I2C_SYSTEST	(0x3c)
 
 /* I2C masks */
 
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 24652c8..5abf454 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -116,6 +116,8 @@
 #define CONFIG_SYS_I2C_BUS		0
 #define CONFIG_SYS_I2C_BUS_SELECT	1
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
+#define CONFIG_I2C_MULTI_BUS		1
+#define CONFIG_I2C_CMD_TREE		1
 
 /*
  * Board NAND Info.
@@ -176,7 +178,7 @@
 		"video=${videospec},mode:${videomode} " \
 		"root=/dev/mtdblock4 rw " \
 		"rootfstype=jffs2\0" \
-	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"loadbootscript=fatload mmc 0 ${loadaddr} reset.scr\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"autoscr ${loadaddr}\0" \
 	"loaduimage=fatload mmc 0 ${loadaddr} uImage.bin\0" \
