diff -uprN u-boot-ti-1_1_4/board/omap3530beagle/clock.c u-boot-ti-revb/board/omap3530beagle/clock.c --- u-boot-ti-1_1_4/board/omap3530beagle/clock.c 2008-02-18 13:09:24.000000000 +0100 +++ u-boot-ti-revb/board/omap3530beagle/clock.c 2008-06-03 16:36:27.000000000 +0200 @@ -164,48 +170,48 @@ void prcm_init(void) - dpll_param_p = dpll_param_p + 2*clk_index + sil_index; + dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; @@ -216,69 +222,67 @@ void prcm_init(void) - dpll_param_p = dpll_param_p + 2*clk_index + sil_index; + dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - dpll_param_p = dpll_param_p + 2*clk_index + sil_index; + dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; diff -uprN u-boot-ti-1_1_4/board/omap3530beagle/config.mk u-boot-ti-revb/board/omap3530beagle/config.mk --- u-boot-ti-1_1_4/board/omap3530beagle/config.mk 2007-11-30 20:54:12.000000000 +0100 +++ u-boot-ti-revb/board/omap3530beagle/config.mk 2008-06-03 16:36:27.000000000 +0200 @@ -2,11 +2,9 @@ # (C) Copyright 2006 # Texas Instruments, # -# SDP3430 board uses OMAP3430 (ARM-CortexA8) cpu +# Begale Board uses OMAP3 (ARM-CortexA8) cpu # see http://www.ti.com/ for more information on Texas Instruments # -# SDP3430 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 -# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 # Physical Address: # 8000'0000 (bank0) # A000/0000 (bank1) @@ -17,7 +15,3 @@ TEXT_BASE = 0x80e80000 -# Handy to get symbols to debug ROM version. -#TEXT_BASE = 0x0 -#TEXT_BASE = 0x08000000 -#TEXT_BASE = 0x04000000 diff -uprN u-boot-ti-1_1_4/board/omap3530beagle/mem.c u-boot-ti-revb/board/omap3530beagle/mem.c --- u-boot-ti-1_1_4/board/omap3530beagle/mem.c 2008-03-12 07:54:33.000000000 +0100 @@ -42,192 +45,38 @@ unsigned int boot_flash_off = 0; -/* StrataNor */ -extern uchar flash_env_get_char_spec(int index); -extern int flash_env_init(void); -extern int flash_saveenv(void); -extern void flash_env_relocate_spec(void); -extern char *flash_env_name_spec; - /* 16 bit NAND */ -extern uchar nand_env_get_char_spec(int index); -extern int nand_env_init(void); -extern int nand_saveenv(void); -extern void nand_env_relocate_spec(void); -extern char *nand_env_name_spec; - -/* OneNAND */ -extern char *onenand_env; -extern uchar onenand_env_get_char_spec(int index); -extern int onenand_env_init(void); -extern int onenand_saveenv(void); -extern void onenand_env_relocate_spec(void); -extern char *onenand_env_name_spec; +extern uchar env_get_char_spec(int index); +extern int env_init(void); +extern int saveenv(void); +extern void env_relocate_spec(void); +extern char *env_name_spec; -/* Global fellows */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) u8 is_nand = 0; -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_FLASH) -u8 is_flash = 0; -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_ONENAND) -u8 is_onenand = 0; -#endif - -char *env_name_spec = 0; -/* update these elsewhere */ -env_t *env_ptr = 0; - -#if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH)) -extern env_t *flash_addr; -#endif #endif /* ENV_IS_VARIABLE */ -/* SDP3430 Board CS Organization - * Two PISMO connections are specified. PISMO1 is first and default PISMO board - * PISMO2 is a 2nd stacked PISMOv2 board and is meant for vendor extensions. - */ -static const unsigned char chip_sel[][GPMC_MAX_CS] = { -/* GPMC CS Indices (ON=0, OFF=1)*/ -/* S8- 1 2 3 IDX CS0, CS1, CS2 .. CS7 */ -/*ON ON ON */{PISMO1_NOR, PISMO1_NAND, PISMO1_ONENAND, DBG_MPDB, 0, 0, 0, 0}, -/*ON ON OFF */{PISMO1_ONENAND, PISMO1_NAND, PISMO1_NOR, DBG_MPDB, 0, 0, 0, 0}, -/*ON OFF ON */{PISMO1_NAND, PISMO1_ONENAND, PISMO1_NOR, DBG_MPDB, 0, 0, 0, 0}, -/*ON OFF OFF */{PISMO2_CS0, PISMO1_ONENAND, PISMO1_NOR, DBG_MPDB, 0, 0, 0, 0}, -/*OFF ON ON*/{PISMO1_NOR, PISMO2_CS1, PISMO1_ONENAND, DBG_MPDB, 0, 0, 0, 0}, -/*OFF ON OFF*/{PISMO1_NOR, PISMO2_CS1, PISMO2_CS0, DBG_MPDB, 0, 0, 0, 0}, -/*OFF OFF ON*/{PISMO2_CS0, PISMO1_NOR, PISMO2_CS1, DBG_MPDB, 0, 0, 0, 0}, -/*OFF OFF OFF*/{PISMO2_CS1, PISMO1_NOR, PISMO2_CS0, DBG_MPDB, 0, 0, 0, 0} -}; - -/* SDP3430 V2 Board CS organization - * Different from SDP3430 V1. Now 4 switches used to specify CS - */ -static const unsigned char chip_sel_sdpv2[][GPMC_MAX_CS] = { -/* GPMC CS Indices (ON=0, OFF=1)*/ -/* S8-1 2 3 4 IDX CS0, CS1, CS2 .. CS7 */ -/*ON ON ON ON*/{PISMO1_NOR, PISMO1_NAND, PISMO1_ONENAND, DBG_MPDB, 0, 0, 0, 0}, -/*ON ON ON OFF*/{PISMO1_ONENAND, PISMO1_NAND, PISMO1_NOR, DBG_MPDB, 0, 0, 0, 0}, -/*ON ON OFF ON */{PISMO1_NAND, PISMO1_ONENAND, PISMO1_NOR, DBG_MPDB, 0, 0, 0, 0}, -/*ON ON OFF OFF*/{PISMO1_NOR, PISMO2_CS0, PISMO2_CS1, DBG_MPDB, 0, 0, 0, 0}, -/*ON OFF ON ON*/{PISMO1_ONENAND, PISMO2_CS0, PISMO2_CS1, DBG_MPDB, 0, 0, 0, 0}, -/*ON OFF ON OFF*/{PISMO1_NAND, PISMO2_CS0, PISMO2_CS1, DBG_MPDB, 0, 0, 0, 0}, -/*ON OFF OFF ON*/{PISMO1_NOR, PISMO2_NAND_CS0, PISMO2_NAND_CS1, DBG_MPDB, 0, 0, 0, 0}, -/*ON OFF OFF OFF*/{PISMO1_ONENAND, PISMO2_NAND_CS0, PISMO2_NAND_CS1, DBG_MPDB, 0, 0, 0, 0} -}; - -/* Values for each of the chips */ -static u32 gpmc_mpdb[GPMC_MAX_REG] = { - MPDB_GPMC_CONFIG1, - MPDB_GPMC_CONFIG2, - MPDB_GPMC_CONFIG3, - MPDB_GPMC_CONFIG4, - MPDB_GPMC_CONFIG5, - MPDB_GPMC_CONFIG6, 0 -}; - -static u32 gpmc_stnor[GPMC_MAX_REG] = { - STNOR_GPMC_CONFIG1, - STNOR_GPMC_CONFIG2, - STNOR_GPMC_CONFIG3, - STNOR_GPMC_CONFIG4, - STNOR_GPMC_CONFIG5, - STNOR_GPMC_CONFIG6, 0 -}; -static u32 gpmc_sibnor[GPMC_MAX_REG] = { - SIBNOR_GPMC_CONFIG1, - SIBNOR_GPMC_CONFIG2, - SIBNOR_GPMC_CONFIG3, - SIBNOR_GPMC_CONFIG4, - SIBNOR_GPMC_CONFIG5, - SIBNOR_GPMC_CONFIG6, 0 -}; -static u32 gpmc_smnand[GPMC_MAX_REG] = { - SMNAND_GPMC_CONFIG1, - SMNAND_GPMC_CONFIG2, - SMNAND_GPMC_CONFIG3, - SMNAND_GPMC_CONFIG4, - SMNAND_GPMC_CONFIG5, - SMNAND_GPMC_CONFIG6, 0 -}; static u32 gpmc_m_nand[GPMC_MAX_REG] = { - M_NAND_GPMC_CONFIG1, - M_NAND_GPMC_CONFIG2, - M_NAND_GPMC_CONFIG3, - M_NAND_GPMC_CONFIG4, - M_NAND_GPMC_CONFIG5, - M_NAND_GPMC_CONFIG6, 0 -}; -static u32 gpmc_pismo2[GPMC_MAX_REG] = { - P2_GPMC_CONFIG1, - P2_GPMC_CONFIG2, - P2_GPMC_CONFIG3, - P2_GPMC_CONFIG4, - P2_GPMC_CONFIG5, - P2_GPMC_CONFIG6, 0 -}; -static u32 gpmc_onenand[GPMC_MAX_REG] = { - ONENAND_GPMC_CONFIG1, - ONENAND_GPMC_CONFIG2, - ONENAND_GPMC_CONFIG3, - ONENAND_GPMC_CONFIG4, - ONENAND_GPMC_CONFIG5, - ONENAND_GPMC_CONFIG6, 0 + M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, 0 }; -/********** Functions ****/ - -/* ENV Functions */ -#ifdef ENV_IS_VARIABLE -uchar env_get_char_spec(int index) -{ - if (!boot_env_get_char_spec) { - puts("ERROR!! env_get_char_spec not available\n"); - } else - return boot_env_get_char_spec(index); - return 0; -} -int env_init(void) -{ - if (!boot_env_init) { - puts("ERROR!! boot_env_init not available\n"); - } else - return boot_env_init(); - return -1; -} -int saveenv(void) -{ - if (!boot_saveenv) { - puts("ERROR!! boot_saveenv not available\n"); - } else - return boot_saveenv(); - return -1; -} -void env_relocate_spec(void) -{ - if (!boot_env_relocate_spec) { - puts("ERROR!! boot_env_relocate_spec not available\n"); - } else - boot_env_relocate_spec(); -} -#endif - @@ -295,135 +144,44 @@ void sdrc_init(void) -void do_sdrc_init_old(u32 offset, u32 early) -{ - u32 common = 0, cs0 = 0, pmask = 0, pass_type, mtype, mono = 0; - - if (offset == SDRC_CS0_OSET) - cs0 = common = 1; /* int regs shared between both chip select */ - - pass_type = IP_DDR; - - /* If this is a 2nd pass init of a CS1, make it contiguous with CS0 */ - if (!early && (((mtype = get_mem_type()) == DDR_COMBO) - || (mtype == DDR_STACKED))) { - if (mtype == DDR_COMBO) { - pmask = BIT2; /* if shared CKE don't use */ - pass_type = COMBO_DDR; /* CS1 config */ - __raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, - SDRC_POWER); - } - make_cs1_contiguous(); - } - -next_mem_type: - if (common) { /* do a SDRC reset between types to clear regs */ - __raw_writel(SOFTRESET, SDRC_SYSCONFIG); /* reset sdrc */ - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait on reset */ - __raw_writel(0, SDRC_SYSCONFIG); /* clear soft reset */ - __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); - /* If its a 3430 ES1.0 silicon, configure WAKEUPPROC to 1 as - per Errata 1.22 */ - /* Need to change the condition to silicon and rev check */ - if(1) - __raw_writel((__raw_readl(SDRC_POWER)) | WAKEUPPROC - , SDRC_POWER); -#ifdef POWER_SAVE - __raw_writel(__raw_readl(SMS_SYSCONFIG) | SMART_IDLE, - SMS_SYSCONFIG); - __raw_writel(SDP_SDRC_SHARING | SMART_IDLE, SDRC_SHARING); - __raw_writel((__raw_readl(SDRC_POWER) | BIT6), SDRC_POWER); -#endif - } - - /* set MDCFG_0 values */ - if ((pass_type == IP_DDR) || (pass_type == STACKED)) { - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0 + offset); - if (mono) /* Stacked with memory on CS1 only */ - __raw_writel(SDP_SDRC_MDCFG_MONO_DDR, SDRC_MCFG_0 + offset); - } else if (pass_type == COMBO_DDR) { /* (combo-CS0/CS1) */ - __raw_writel(SDP_COMBO_MDCFG_0_DDR, SDRC_MCFG_0 + offset); - } else if (pass_type == IP_SDR) { /* ip sdr-CS0 */ - __raw_writel(SDP_SDRC_MDCFG_0_SDR, SDRC_MCFG_0 + offset); - } - - /* Set ACTIM values */ - if (cs0) { - __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - } else { - __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_1); - __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1); - } - __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL + offset); - - /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0 + offset); - sdelay(5000); /* supposed to be 100us per design spec for mddr/msdr */ - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0 + offset); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0 + offset); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0 + offset); - - /* Set MR0 values */ - if (pass_type == IP_SDR) - __raw_writel(SDP_SDRC_MR_0_SDR, SDRC_MR_0 + offset); - else - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0 + offset); - - /* setup 343x DLL values (DDR only) */ - if (common && (pass_type != IP_SDR)) { - __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); - sdelay(0x2000); /* give time to lock, at least 1000 L3 */ - } - sdelay(0x1000); - - if (mono) /* Used if Stacked memory is on CS1 only */ - make_cs1_contiguous(); /* make CS1 appear at CS0 */ - - if (mem_ok()) - return; /* STACKED, other configured type */ - ++pass_type; /* IPDDR->COMBODDR->IPSDR for CS0 */ - goto next_mem_type; @@ -448,236 +206,58 @@ void enable_gpmc_config(u32 * gpmc_confi * Init GPMC for x16, MuxMode (SDRAM in x32). * This code can only be executed from SRAM or SDRAM. *****************************************************/ -#ifdef CONFIG_BEAGLE_REV1 -#else -#endif - diff -uprN u-boot-ti-1_1_4/board/omap3530beagle/nand.c u-boot-ti-revb/board/omap3530beagle/nand.c --- u-boot-ti-1_1_4/board/omap3530beagle/nand.c 2008-02-18 11:07:13.000000000 +0100 +++ u-boot-ti-revb/board/omap3530beagle/nand.c 2008-06-03 16:36:27.000000000 +0200 @@ -29,7 +29,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) +#if defined(CONFIG_CMD_NAND) #include @@ -39,11 +39,12 @@ volatile unsigned long gpmc_cs_base_add; +/* int nand_unlock(struct mtd_info *mtd, unsigned long off, unsigned long size) { register struct nand_chip *this = mtd->priv; @@ -58,6 +59,7 @@ int nand_unlock(struct mtd_info *mtd, un ndelay (100); return 0; } +*/ @@ -109,30 +111,31 @@ static int omap_nand_wait(struct mtd_inf /* * omap_nand_dev_ready - Wait for the NAND device to exit busy state * by polling on RDY/BSY signal * @mtd: MTD device structure - */ + */ +#if 0 } - +#endif #ifdef CFG_NAND_WIDTH_16 /** @@ -143,16 +146,17 @@ static int omap_nand_dev_ready(struct mt @@ -231,26 +235,12 @@ static void omap_hwecc_init(struct nand_ /* - * omap_compare_ecc - This function compares two ECC's and indicates if there is an error. - * If the error can be corrected it will be corrected to the buffer - * @ecc_data1: ecc code from nand spare area - * @ecc_data2: ecc code from hardware register obtained from hardware ecc - * @page_data: page data - */ -static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ - u8 *ecc_data2, /* read from register */ - u8 *page_data) -{ - return 0; -} - -/* * omap_correct_data - Compares the ecc read from nand spare area with ECC registers values * and corrects one bit error if it has occured * @mtd: MTD device structure @@ -406,46 +394,48 @@ void omap_nand_switch_ecc(struct mtd_inf * Members with a "?" were not set in the merged testing-NAND branch, * so they are not set here either. */ int board_nand_init(struct nand_chip *nand) { + nand->IO_ADDR_R = (int *) gpmc_cs_base_add + GPMC_NAND_DAT; + nand->IO_ADDR_W = (int *) gpmc_cs_base_add + GPMC_NAND_CMD; - nand->IO_ADDR_R = gpmc_cs_base_add + GPMC_NAND_DAT; - nand->IO_ADDR_W = gpmc_cs_base_add + GPMC_NAND_CMD; + return 0; +} diff -uprN u-boot-ti-1_1_4/board/omap3530beagle/omap3530beagle.c u-boot-ti-revb/board/omap3530beagle/omap3530beagle.c --- u-boot-ti-1_1_4/board/omap3530beagle/omap3530beagle.c 2008-04-02 10:12:05.000000000 +0200 +++ u-boot-ti-revb/board/omap3530beagle/omap3530beagle.c 2008-06-16 13:45:05.000000000 +0200 @@ -995,20 +1007,20 @@ int dram_init(void) MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 - MMC2_WP*/\ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8 - LCD_ENBKL*/\ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE */\ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1 */\ + MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | EN | M0)) /*SYS_CLKOUT1 */\ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB1_CLK*/\ - MUX_VAL(CP(ETK_D0_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA0*/\ - MUX_VAL(CP(ETK_D1_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA1*/\ - MUX_VAL(CP(ETK_D2_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA2*/\ - MUX_VAL(CP(ETK_D3_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA7*/\ - MUX_VAL(CP(ETK_D4_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA4*/\ - MUX_VAL(CP(ETK_D5_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA5*/\ - MUX_VAL(CP(ETK_D6_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA6*/\ - MUX_VAL(CP(ETK_D7_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA3*/\ - MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DIR*/\ - MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_NXT*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB1_STP*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | EN | M3)) /*HSUSB1_CLK*/\ + MUX_VAL(CP(ETK_D0_ES2 ), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA0*/\ + MUX_VAL(CP(ETK_D1_ES2 ), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA1*/\ + MUX_VAL(CP(ETK_D2_ES2 ), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA2*/\ + MUX_VAL(CP(ETK_D3_ES2 ), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA7*/\ + MUX_VAL(CP(ETK_D4_ES2 ), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA4*/\ + MUX_VAL(CP(ETK_D5_ES2 ), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA5*/\ + MUX_VAL(CP(ETK_D6_ES2 ), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA6*/\ + MUX_VAL(CP(ETK_D7_ES2 ), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA3*/\ + MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DIR*/\ + MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_NXT*/\ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | EN | M4)) /*GPIO_24*/\ MUX_VAL(CP(ETK_D15), (IEN | PTU | EN | M4)) /*GPIO_29*/\ MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ diff -uprN u-boot-ti-1_1_4/board/omap3530beagle/sys_info.c u-boot-ti-revb/board/omap3530beagle/sys_info.c --- u-boot-ti-1_1_4/board/omap3530beagle/sys_info.c 2007-11-30 21:06:57.000000000 +0100 +++ u-boot-ti-revb/board/omap3530beagle/sys_info.c 2008-06-03 16:36:27.000000000 +0200 @@ -38,8 +40,8 @@ ***************************************************************************/ u32 get_gpmc0_type(void) { - // Default OneNAND - return (1); + // Default NAND + return (2); } u32 brev = get_board_rev(); - char cpu_3430s[] = "3430"; - char mem_sdr[] = "mSDR"; /* memory type */ - char mem_ddr[] = "mDDR"; + char cpu_3430s[] = "3530"; + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "LPDDR";