Hi,
I'm trying to debug some performance issues related to odd i-cache
misses on the Beagleboard. The Cortex-A8 docs have some very
interesting instructions that allow you to look at the contents of
the caches, TLBs, etc (section 3.2.74 of the A8 TRM). However, no
matter how I try, I cannot get these instructions to work - they
always raise an undefined instruction exception.
Here is a sample snippet of code that I would like to run:
void dump_icache_tags() {
int set, index;
for (index = 0; index < (32*1024 / 64 / 4); index++) {
for (set = 0; set < 4; set++) {
uint32_t setway = set << 30 | index << 6;
uint32_t tag, data;
asm volatile (
"mcr p15, 0, %2, c15, c3, 6\n\t"
"mrc p15, 0, %0, c15, c1, 0\n\t"
"mcr p15, 0, %2, c15, c3, 7\n\t"
"mrc p15, 0, %1, c15, c1, 0\n\t"
: "=r"(tag), "=r"(data)
: "r"(setway)
);
printf("%4d/%d: 0x%08x 0x%08x\n", index, set, tag, data);
}
}
}
I've tried from within Linux, u-boot and even in x-load, all giving
the same result of undefined instruction-ness.
It appears that these co-processor registers are inaccessible,
because I am not in a Secure mode. The OMAP on the Beagleboard
claims to support the Security Extensions (according to Processor
Feature Register 1 - c0, c1, 1). I have read that the Beagleboard
parts are GP though, not HS.
Does this mean that there is no way to access _anything_ that needs
Secure mode?
This seems odd, as that also means that you cannot change (almost)
all of the useful bits in the Auxilliary Control Register (c1, c0,
1), as they can only be modified from a Secure state.
Does anyone know if it is possible to get at either the Auxilliary
Control Register, or the cache debug registers on the Beaglebaord?
Thanks,
Bernard.