I try to add two numbers with FPGA. The code of my apb_adder is this:
module apb_adder (
input wire PCLK,
input wire PRESETN,
input wire PSEL,
input wire PENABLE,
input wire PWRITE,
input wire [31:0] PADDR,
input wire [31:0] PWDATA,
output reg [31:0] PRDATA,
output wire PREADY
);
// ============================================================
// Main registers
// ============================================================
reg [31:0] reg_a;
reg [31:0] reg_b;
wire [31:0] sum;
assign sum = reg_a + reg_b;
// Peripheral is always ready
assign PREADY = 1'b1;
// ============================================================
// DEBUG REGISTERS
// ============================================================
// Last observed PSEL
reg [31:0] debug_psel;
// Last observed PENABLE
reg [31:0] debug_penable;
// Last observed PWRITE
reg [31:0] debug_pwrite;
// Last observed PADDR
reg [31:0] debug_paddr;
// Last observed PWDATA
reg [31:0] debug_pwdata;
// Indicates that a valid APB WRITE was observed
reg [31:0] debug_write_seen;
// ============================================================
// APB WRITE + DEBUG
// ============================================================
always @(posedge PCLK or negedge PRESETN) begin
if (!PRESETN) begin
reg_a <= 32'h00000000;
reg_b <= 32'h00000000;
debug_psel <= 32'h00000000;
debug_penable <= 32'h00000000;
debug_pwrite <= 32'h00000000;
debug_paddr <= 32'h00000000;
debug_pwdata <= 32'h00000000;
debug_write_seen <= 32'h00000000;
end
else begin
// ----------------------------------------------------
// Capture APB signals whenever PCLK arrives
// ----------------------------------------------------
debug_psel <= {31'b0, PSEL};
debug_penable <= {31'b0, PENABLE};
debug_pwrite <= {31'b0, PWRITE};
debug_paddr <= PADDR;
debug_pwdata <= PWDATA;
// ----------------------------------------------------
// Detect a valid APB WRITE
// ----------------------------------------------------
if (PSEL && PENABLE && PWRITE) begin
debug_write_seen <= 32'hDEADBEEF;
case (PADDR[7:0])
// Register A
8'h00:
reg_a <= PWDATA;
// Register B
8'h04:
reg_b <= PWDATA;
default:
begin
// No action
end
endcase
end
end
end
// ============================================================
// APB READ
// ============================================================
always @(*) begin
case (PADDR[7:0])
// ----------------------------------------------------
// Main registers
// ----------------------------------------------------
8'h00:
PRDATA = reg_a;
8'h04:
PRDATA = reg_b;
8'h08:
PRDATA = sum;
// ----------------------------------------------------
// Debug registers
// ----------------------------------------------------
// 0x0C = valid write detected?
8'h0C:
PRDATA = debug_write_seen;
// 0x10 = last PSEL
8'h10:
PRDATA = debug_psel;
// 0x14 = last PENABLE
8'h14:
PRDATA = debug_penable;
// 0x18 = last PWRITE
8'h18:
PRDATA = debug_pwrite;
// 0x1C = last PADDR
8'h1C:
PRDATA = debug_paddr;
// 0x20 = last PWDATA
8'h20:
PRDATA = debug_pwdata;
default:
PRDATA = 32'h00000000;
endcase
end
endmodule
But my attempts was unsuccessful. Is there any guy to help me?