I have a new question that I’m hoping @keck9939 will know the answer 
I have been fumbling around on the internet trying to find the microsemi/micropchip IP drivers, I can find some in example projects, here for example: SoftConsole/riscv-simple-baremetal-bootloader/drivers at master · RISCV-on-Microsemi-FPGA/SoftConsole · GitHub
Is there a repository somewhere, or some way of getting softconsole to read a hardware design and set everything up like the Xilinx tools do?
More here: platform/drivers/fpga_ip at main · polarfire-soc/platform · GitHub
I wonder where the originals come from!
I’m unaware of anything beyond what you have already found. I’m not sure what Vivado can do, but I don’t think there is any ability of SoftConsole to do more than read in a configuration generated by the MSS Configurator.
PolarFire comes to Microchip via several mergers. My impression is that Microchip is now making an effort to make these more accessible and easier to use, but it may take some time.
You found it. This is the repository where the PolarFire SoC bare metal driver are kept (platform/drivers/fpga_ip at main · polarfire-soc/platform · GitHub)
Hi guys, thanks for the replies.
Super, I thought it must be me being thick!
With the Xilinx tools you hand off the hardware design to the software IDE, relevant drivers are then added to the project, addresses set etc. If you update the hardware design the software project also updates, it is all automagic.
I wonder where the source of the drivers for the Microchip IP is though?
There are many more ip blocks than are in this PolarFire repository, at the basics just headers for the register addresses to use with the HAL would be useful.
For example, In the AXI bare metal demo project we also have the driver for the AXI DMA Controller, this is not available in that PolarFire repo.
polarfire-soc-bare-metal-examples/driver-examples/fpga-ip/CoreAXI4DMAController/mpfs-coreaxi4dma-stream/src/platform/drivers/fpga_ip/CoreAXI4DMAController at main · polarfire-soc/polarfire-soc-bare-metal-examples · GitHub
What I am working towards is getting AXI streaming working, to be honest as the day progressed the driver level is probably the least of my problems
Generating the ref design to use with the bare metal AXI streaming example and then programming it causes the DDR training to halt at 80%, the demo code will not start, the main() of the 51 is never called. Need to solve this, or put in an issue, maybe it is not supported on the disco board yet even though it looks like the ref design supports it.
This is all Fire related though, I want to get some AXI Streaming HLS designs ported over from Vitis HLS to run on the Fire, I think it may take some time…
Cheers
Andy
I feel your pain my friend! Although I wiil probably continue to moan, at least quietly, about Vivado
or FPGA tools in general, Libero does seem to rate quite close to the bottom of the bunch,
based in part of your and my own, albeit limited, observations.
I’m happy to see you’re making progress though; strangely comforting. 
In the meantime, I think I’ll be keeping to using Libero as an elaborate Gateware viewer, hehe.
It’s probably easier to just make custom designs work on a Zynq based build and then port
the code, once they validate in Vivado / Vitis.
I think you need to tie the unused inputs either high or low depending on whatever won’t generate an interrupt to the MSS. Right-click on the input pin and then select Tie High or Tie Low menu item.
-Tim