I have given up on the SPI interface to read out my LTC2500-32 ADC.
I really could not make the PRU produce any SPI output. I lost quite some
time over it, but the best I would have gotten is only 48 Mbps, and I need
100 Mbps when I run the ADC at full speed. I had some leftover space in the
CPLD that creates the sample rate, so I built a 100 MHz 32bit SPI receiver.
Since the PRU1 can read just a 8 bit field over the fast interface, I read
each sample in 4 bytes and shift/paste it together to an int32.
That works, and I could even read 3 ADCs in real time.
Sometimes my BBB does not boot any more. I traced it to the connection
of PRU1.__r31.0. This is also used for boot medium select.
I have obeyed the rule to drive my buffers only when SYS_RESET_n is high.
Probing with the scope showed that SYS_RESET_n is really a ramp that takes
14 msec to rise. If you use that as an input to a digital gate, all sorts of
miraculous things can happen. In particular, it is undefined when the
AM335x, the LAN4710A or the external logic consider reset de-asserted
relatively to each other.
We have a classical race condition here. The board designers have changed
the timing capacitor from 1u to 2.2u in revision A6 since there seemed to be
an issue. Tomorrow, I'll spend an additional timer to delay further the
activation of my circuit.
Executive summary: Qualifying the driving of some IO-Pins with SYS_RESET_n
is not enough, esp. because the CPU just STARTS execution on SYS_RESET_n passive.
It could start later than a cape.
Also, the grounding scheme is an EMC nightmare, with just two GND pins on P8,
lumped together at one end with a lot of high speed pins on the other end of P8.
Using the screws in the 4 corners can really help signal quality.