Where can I find the format of the cape EEPROM pin usage section for the BeagleBone AI? I need to know the ordering of the pins as well as the format of each pin’s 16-bit field.
From what I could figure out on my own the BBB pins are in GPIO order, with the non-muxed AINx pins at the end of the table. Can anyone confirm that this same ordering applies to the BBAI? How are the a/b pins handled (such as 9.19a/b)?
It seems that the BBAI pin bitfield’s format must differ from the BBB since the AM572x has a 4-bit muxmode field, whereas the AM335x has only 3 bits. Has the BBAI’s EEPROM format been posted anywhere?
Thanks,
Diane
Where can I find the format of the cape EEPROM pin usage section for the BeagleBone AI? I need to know the ordering of the pins as well as the format of each pin’s 16-bit field.
From what I could figure out on my own the BBB pins are in GPIO order, with the non-muxed AINx pins at the end of the table. Can anyone confirm that this same ordering applies to the BBAI? How are the a/b pins handled (such as 9.19a/b)?
It seems that the BBAI pin bitfield’s format must differ from the BBB since the AM572x has a 4-bit muxmode field, whereas the AM335x has only 3 bits. Has the BBAI’s EEPROM format been posted anywhere?
This feature of the spec was never utilized.
Regards
Are there any plans to implement this in the future? If not, is the device tree the only way to set up the pin muxing?
Are there any plans to implement this in the future?
No.
If not, is the device tree the only way to set up the pin muxing?
U-boot sets up the device tree and initial pin mux. Using the device tree configured by u-boot is the simplest way to set the pinmux, but you can also change the default pin muxing in u-boot outside of the device tree–just make sure the kernel doesn’t change it by having a device tree that doesn’t match.
Thanks very much for your quick responses, Jason and Robert, I appreciate the assistance.