Hi,
I’ve searched on spreadsheets and on the git repo and it doesn’t seem like the ADC is mapped at all. I saw there was the MCU pins as MCU_ADC0_AIN*, but no where is it mapped.
Is it something that I could do myself or is it locked in some ways?
ADC is enabled out of the box…
voodoo@bbai64-02:~$ iio_info
Library version: 0.24 (git tag: v0.24)
Compiled with backends: local xml ip usb
IIO context created with local backend.
Backend version: 0.24 (git tag: v0.24)
Backend description string: Linux bbai64-02 5.10.145-ti-arm64-r72 #1bullseye SMP Sun Nov 6 02:37:37 UTC 2022 aarch64
IIO context has 2 attributes:
local,kernel: 5.10.145-ti-arm64-r72
uri: local:
IIO context has 2 devices:
iio:device0: TI-am335x-adc.1.auto (buffer capable)
8 channels found:
voltage0: (input, index: 0, format: le:u12/16>>0)
1 channel-specific attributes found:
attr 0: raw value: 43
voltage1: (input, index: 1, format: le:u12/16>>0)
1 channel-specific attributes found:
attr 0: raw value: 44
voltage2: (input, index: 2, format: le:u12/16>>0)
1 channel-specific attributes found:
attr 0: raw value: 44
voltage3: (input, index: 3, format: le:u12/16>>0)
1 channel-specific attributes found:
attr 0: raw value: 45
voltage4: (input, index: 4, format: le:u12/16>>0)
1 channel-specific attributes found:
attr 0: raw value: 43
voltage5: (input, index: 5, format: le:u12/16>>0)
1 channel-specific attributes found:
attr 0: raw value: 44
voltage6: (input, index: 6, format: le:u12/16>>0)
1 channel-specific attributes found:
attr 0: raw value: 44
voltage7: (input, index: 7, format: le:u12/16>>0)
1 channel-specific attributes found:
attr 0: raw value: 686
1 buffer-specific attributes found:
attr 0: data_available value: 0
No trigger on this device
iio:device1: TI-am335x-adc.2.auto (buffer capable)
8 channels found:
voltage0: (input, index: 0, format: le:u12/16>>0)
1 channel-specific attributes found:
attr 0: raw value: 45
voltage1: (input, index: 1, format: le:u12/16>>0)
1 channel-specific attributes found:
attr 0: raw value: 696
voltage2: (input, index: 2, format: le:u12/16>>0)
1 channel-specific attributes found:
attr 0: raw value: 693
voltage3: (input, index: 3, format: le:u12/16>>0)
1 channel-specific attributes found:
attr 0: raw value: 694
voltage4: (input, index: 4, format: le:u12/16>>0)
1 channel-specific attributes found:
attr 0: raw value: 698
voltage5: (input, index: 5, format: le:u12/16>>0)
1 channel-specific attributes found:
attr 0: raw value: 698
voltage6: (input, index: 6, format: le:u12/16>>0)
1 channel-specific attributes found:
attr 0: raw value: 695
voltage7: (input, index: 7, format: le:u12/16>>0)
1 channel-specific attributes found:
attr 0: raw value: 695
1 buffer-specific attributes found:
attr 0: data_available value: 0
No trigger on this device
Need to better document which pins are tied where…
Regards,
Thank you!
Sorry for those kinds of silly questions!
btw, here’s the pin mapping…
&tscadc0 {
/* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */
adc {
ti,adc-channels = <0 1 2 3 4 5 6>;
};
};
&tscadc1 {
/* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */
adc {
ti,adc-channels = <0>;
};
};
Regards,
2 Likes
Hi @RobertCNelson, I have a somewhat related question regarding using the ADC with a dedicated R5F core. It is my understanding that we need to pinmux pins to the device but, prevent Linux from using the device. Is there a provision for this type of use case in the device tree overlay system? Do you know of a good introductory text (or source code) we could read to learn about using overlays with heterogeneous multicore SoCs?
Thanks
EDIT: This article seems to explain the concept …
Device tree partitioning for multicore, multi-OS embedded software designs - Embedded.com
Not sure if this is implemented yet.
1 Like