I’m working on a low-level kernel for the Beaglebone Black. I’ve gotten to a point in my project where I want to specify an IRQ handler and enable interrupts.
According to the technical reference manual (section 26.1.4), there are two primary locations you can load a disk image to. The first is what they call “Public ROM” which seems pretty straightforward. You load your image to address 0x20000 and the interrupt vector table is the first thing which gets encountered.
The second location you can load an image is “Public RAM” (which I’m using). This starts executing at 0x402F0400 and you get 109kb of space for your application. The weird part is, the interrupt vector table appears to be located super far away from the entrypoint, at location 0x4030CE00. This is more than 109kb away, so it can’t be included in the image which gets flashed to the device.
I am at a loss about how to get an instruction to that particular location in memory since my image fundamentally can’t be that size. Any guidance on how to setup the IVT for Public RAM would be greatly appreciated.
Thank you for your time!
I’ve solved my own problem and thought I’d share for any lost soul in the future who seeks these answers.
If you look at the technical reference manual for the am355x section 26-3 it shows an interrupt vector table which exists wildly far away from your application entrypoint. Upon closer inspection, I realized some entries are listed twice. This is because the interrupt vector table is actually a bunch of indirection.
If you want to set the IRQ branch address you specify the address at location 0x4030_CE38
If you want to set the pre-fetch abort address you specify the address at location 0x4030_CE2C
// Set the IRQ handler to the entrypoint of the application + 24 bytes
*(0x4030_CE38 as *mut u32) = 0x402F_0400 + 0x18;
I assumed I needed to write an actual branch instruction to those locations. Which is where my confusion started. So if you are building a low-level kernel and are working with interrupts, just remember that the vector table can be updated by simply writing the correct address to your handler based on the vector table in the reference manual (not an actual branch instruction).
Your handler needs the keyword interrupt to save the registers so when the vector occurs whatever was running isn’t corrupted
Besides interrupt vector table don’t forget exceptions they need a vector as well as in bus error or address error
Here’s a brief reference you should look for interrupt code to verify and the correct arm programming guide
You could look at the TI starterware code for examples of setting up the interrupt table and the code at the tables.
Yes I agree. Make sure to look at startup assembler language file many times vectors are in it. Start or start-up. Asm
Thank you everyone! I appreciate the responses.
After days of trial and error I managed to setup the IVT and configure one of the timers to fire an interrupt on overflow. For me, I found this resource pretty helpful: https://android.googlesource.com/kernel/lk/+/upstream-master/platform/am335x - it appears to be the embedded android kernel ported to the beaglebone. They have some good interrupt stuff in there, as well as device-specific peripheral drivers.
I’m struggling now with “de-triggering” an interrupt after it fired. So my timer fires one interrupt and then the IRQSTATUS_RAW keeps its value, no matter how many ways I try to reset it. So I am only handling it once.
I feel I’m close though. Hopefully the resources shared + the anrdoid kernel I found will shed some light on how to correctly process an interrupt.
If the interrupt is a level interrupt, your interrupt handling procedure needs to start clearing the interrupt starting at the source of the interrupt otherwise the interrupt will trigger again.