[beagleboard] BeagleBoard Data Acquisition Platform

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1

Hey all,

For those who care, I have drawn up designs for the second iteration of my
BeagleBoard-based data acquisition platform[1].

This new design features 32 DAC channels and 32 ADC channels, both with 16-bit
resolution. The ADC sampling rate is a little lower than I would have liked
at 100ksamples/second (with the SPI bus running at 2MHz), but this should be
more than enough for most tasks. The DACs on the other hand can run at up to
20MHz (limited by the level shifters). Additionally, the board now exposes 8
GPIO pins behind a level shifter, making it possible to directly interface with
standard 5V TTL levels.

The ADC part I'm using is TI's ADS8344 and the DAC is TI's DAC8568. The level
shifters are TI's TXB0108 and the demultiplexer used for chip select is TI's
SN74AHC139. Altogether, the board is quite expensive. Each of the four DACs are
$25.00 and each of the four ADCs are $10. Thus, a fully populated board is
about $150 in parts alone. Far more expensive than I was hoping for, but it
seems that these prices are pretty common in the world of converters.

The board is designed to fit on a BeagleBoard XM-style expansion connector and
thus sits beneath the BeagleBoard.

One issue I encountered with the last design[2] was the large in-rush of
current at startup which seems to cause the BeagleBoard to brown-out. This
makes it necessary to remove the board while starting up the BeagleBoard. While
I'm not certain of the cause of this, I suspect that the largish filter
capacitors (330uF IIRC) on the voltage rails might be at least in part to
blame. Anyone have any thoughts on this? I've reduced the value of these to
100uF, but it would be nice to have a slightly more certain solution.

If anyone has any comments, I would love to hear them. I think this design is
orders of magnitude better than the original, but there is no doubt still room
for improvement. In particular, I would love to hear suggestions about the PCB
layout. I took some steps to ensure good analog characteristics (e.g.
maintaining continuity in the ground plane), but I'm sure there are other
things that could be improved. Moreover, the reference supply is little more
than a RC filter. Is this sufficient or could there be a better option here
(perhaps an active voltage reference or Zener regulator)?

Anyways, I look forward to hearing any feedback that folks have. Thanks for
listening.

Cheers,

- Ben

[1] http://goldnerlab.physics.umass.edu/wiki/BeagleBoardDaq
[2] http://goldnerlab.physics.umass.edu/wiki/BeagleBoardDaq/Version1

2

Does it have an eeprom so it can be ID'd by uboot/kernel?

regards,

Koen

3

It does now. Let me know if there's anything else I can add. Thanks for
the suggestion!

- Ben

4

Ben Gamari <bgamari@...> writes:

Hey all,

For those who care, I have drawn up designs for the second iteration of my
BeagleBoard-based data acquisition platform[1].

This new design features 32 DAC channels and 32 ADC channels, both with 16-bit
resolution. The ADC sampling rate is a little lower than I would have liked
at 100ksamples/second (with the SPI bus running at 2MHz), but this should be
more than enough for most tasks. The DACs on the other hand can run at up to
20MHz (limited by the level shifters). Additionally, the board now exposes 8
GPIO pins behind a level shifter, making it possible to directly interface with
standard 5V TTL levels.

The ADC part I'm using is TI's ADS8344 and the DAC is TI's DAC8568. The level
shifters are TI's TXB0108 and the demultiplexer used for chip select is TI's
SN74AHC139. Altogether, the board is quite expensive. Each of the four DACs are
$25.00 and each of the four ADCs are $10. Thus, a fully populated board is
about $150 in parts alone. Far more expensive than I was hoping for, but it
seems that these prices are pretty common in the world of converters.

The board is designed to fit on a BeagleBoard XM-style expansion connector and
thus sits beneath the BeagleBoard.

One issue I encountered with the last design[2] was the large in-rush of
current at startup which seems to cause the BeagleBoard to brown-out. This
makes it necessary to remove the board while starting up the BeagleBoard. While
I'm not certain of the cause of this, I suspect that the largish filter
capacitors (330uF IIRC) on the voltage rails might be at least in part to
blame. Anyone have any thoughts on this? I've reduced the value of these to
100uF, but it would be nice to have a slightly more certain solution.

If anyone has any comments, I would love to hear them. I think this design is
orders of magnitude better than the original, but there is no doubt still room
for improvement. In particular, I would love to hear suggestions about the PCB
layout. I took some steps to ensure good analog characteristics (e.g.
maintaining continuity in the ground plane), but I'm sure there are other
things that could be improved. Moreover, the reference supply is little more
than a RC filter. Is this sufficient or could there be a better option here
(perhaps an active voltage reference or Zener regulator)?

Anyways, I look forward to hearing any feedback that folks have. Thanks for
listening.

Cheers,

- Ben

[1] http://goldnerlab.physics.umass.edu/wiki/BeagleBoardDaq
[2] http://goldnerlab.physics.umass.edu/wiki/BeagleBoardDaq/Version1

Hi, Ben,

Glad to see your message and know that you are developing a DAQ board for
beagleboard, which is what we are planning to do in the next a few months.

Although the 32 channels of ADC and 32 channels of DAC are too many for us, we
may have some collabration to improve your board, if it is possible.

Does your DAQ board come with digital IO pins (5V TTL)? I found the links you
provided do not work,

[1] http://goldnerlab.physics.umass.edu/wiki/BeagleBoardDaq
[2] http://goldnerlab.physics.umass.edu/wiki/BeagleBoardDaq/Version1

Would you mind to share these document with us? Or email to me. Any comments
and suggestions are much appreciated.

Best regards,

Dan

5

This is really good product. Some commercial analog input/output devices are sold by $500 with only 16 channels.

6

Your links appear to be broken so I couldn't see the PCB layout, but you should, in general, always use an external commercial voltage reference ( if one is not provided internally) rather than depending on power supply voltage. Otherwise, you are probably throwing away half of those 16 bits!

Hope you can fix those links.

Cheers.

7

Hi,
your links are broken… Hope you fix it…

Thanks

8

How many people here are serious about making an ADC cape for the BBB? One thing we could do is create a wiki and do it as a
group effort.

It sure worked for Linux.

I myself would like a bank of ADS8344 chips - On the BBB that would entail sending and receiving digital signals on the GPIO.
And - I hasten to mention, I am not an ee designer - AI SW is my thing. - BUT I feel strongly that this project is easily do-able.

So please leave a response here if you are interested in participating.

Here are a few tasks: (I am mainly interested in ADC.):

  1. get digital signalling protocol from ads8344 spec sheet (ti.com)
  2. get code to IO the GPIO pins.
  3. post some questions on ti.com forums - get intouch with adc engineer there. get her advice.
  4. V ref circuit.
  5. choose language, Python fast enough?
  6. order chips and interface boards for SMD type.
  7. solder chips. (easy)
  8. connect to GPIO.
  9. start sending signals and do a conversion. (ADC)
  10. write SW to store values in data structures.

Anyone on?
jb

email:
haiticare2011 at gmail daht kom.

9

32 channels is - a lot. At 16-bit, too. On the other hand, the actual sample rate is quite low: 200K sample/sec
This sounds like the backbone of a 32-channel audio mixing desk. Which is fine, if that’s what you are into…

Personally, I’d prefer 2 [or even 1] ADC channel, with a MUCH higher sample rate. Say: 120 M sample/sec.
Sure there are faster ADC’s - but original [parallel] ATA cables were rated to 133MHz, so I’m aiming for a spec
that reduces the need for matching length tracks etc.

You’d probably need an FPGA to interface that with a Beagleboard, or Beaglebone Black [my device].

– Alan

10

My dear Penguin,

Yes, the desired SPS rate is rather low, as I was feeling limited by the actual possibilities here. I am a pattern recognizer

bird myself, and looking primarily at 2 problems:

  1. Non Invasive medical diagnostics. These use NIR, electronic noses, and perhaps EEG, EMG.

  2. The quantum mechanical nature of consciousness. These onvolve detecting signals like 1 above - coupled with AI, like 1.

Both of these aims ask for rather many channels with rather low speeds. Why? Because the combinatorial pattern recognizer asks for

a unique signature across many channels. Example (rough): Suppose you can detect a signal in the NIR at .8 microns. It has 32 levels,

IOW a crappy signal. That’s 2 exp 5. Now suppose you have 8 of these channels. Suddenly, the degree of freedom is 2 exp 40. IOW

the signal is more unique, and noise has a harder time jamming.

That’s the justification for many channels. Now, I wonder what your desire for high speed is. What would you use it for? I looked at the

microchip pic24fj128gc010. That can do only 20 MSPS, though. (from memory) OTOH, I have a Tektronix scope that can do 10 GSPS on 4 channels.

So I am not aware of ADC chips that fast - It’s an interesting problem though - How would you design such a thing?

Let’s see - 120 MSPS would entail 240 MB/s at 16 bit res. (just for argument here.). That seems well within SATA 3 and USB 3 type rates these days.

But this is not a vanilla ADC chip.

A SAR-type design (speaking very roughly) will require 240x16x10exp6 comparisons per sec. That’s a comparator speed of 4x10exp9 per sec -

A comparator can get a speed (realistically) of 10 nanosec. Thats 10 exp 8 comparisons per sec. So 4x10exp9/10exp8 = 40 comparators.

Seems doable, but I have shied away from it as being beyond my practicality (and needs) - since I am not skilled in high speed circuit design, as well as

the issue of handling and data storage at the CPU level.

I estimate that, in order to get that rate, you would have to build a desk top super computer, made up of DSP board multiprocessors. (idea to get away from

circuit design.)

Then the DSP memory would be connected to 1TB SSD drives to collect data. At this rate, you are going to accumulate a gB in 4 seconds, so a 1TB SSD will be good for
an hour of data collection.

What do you want this speed for? High speed events?

JB

11

My dear Penguin,

Yes, the desired SPS rate is rather low, as I was feeling limited by the actual possibilities here. I am a pattern recognizer

bird myself, and looking primarily at 2 problems:

  1. Non Invasive medical diagnostics. These use NIR, electronic noses, and perhaps EEG, EMG.

  2. The quantum mechanical nature of consciousness. These onvolve detecting signals like 1 above - coupled with AI, like 1.

Both of these aims ask for rather many channels with rather low speeds. Why? Because the combinatorial pattern recognizer asks for

a unique signature across many channels. Example (rough): Suppose you can detect a signal in the NIR at .8 microns. It has 32 levels,

IOW a crappy signal. That’s 2 exp 5. Now suppose you have 8 of these channels. Suddenly, the degree of freedom is 2 exp 40. IOW

the signal is more unique, and noise has a harder time jamming.

That’s the justification for many channels. Now, I wonder what your desire for high speed is. What would you use it for? I looked at the

microchip pic24fj128gc010. That can do only 20 MSPS, though. (from memory) OTOH, I have a Tektronix scope that can do 10 GSPS on 4 channels.

So I am not aware of ADC chips that fast - It’s an interesting problem though - How would you design such a thing?

http://www.ti.com/tool/adc12d1800rb

Regards,
John

12

And only 2000$ too!

j

13

And only 2000$ too!

j

Yeah, but it is really amazing piece of technology running at 3.6GSPS. BTW, most of the DSP is done in the FPGA.

Regards,
John

14

Aah now I see. Using multiple channels to search for signals buried in noise.
Like the phase array of antennas used in the WERA radar system: http://www.aslenv.com/WERA.html

Whereas my own desires are based on the Red Pitaya: http://redpitaya.com
A lovely bit of kit, if you can spare $500+ and don’t mind Yet Another ARM Processor [built into the FPGA chip]…

For more modest requirements, this should be do-able as an extension to the Beaglebone series.
A quick check of TI’s selection table found the ADS4145 and ADS4245 [1 and 2 channel version, 125M, 14-bit].
Analog Devices have the AD9648-125, and Linear Technology have the LTC2145-14.
Feel free to look them up if you’re curious about how they work: I consider much of that “magic smoke”

As for WHY I want one - primarily, RF signal analysis. 120 Msample/sec lets you grab from DC to 30MHz, with simple filtering.
You can also monitor FM bands [88-108MHz] which fall in the 2nd Nyquist sample zone and get “reflected” down to 12 - 32 MHz
Oh, and amateur radio and weather satellites, in the band 140 - 150 MHz, can be under sampled at 25 - 30MHz.

Not to mention being able to cover 40MHz of bandwidth, such as WiFi, by adding a mixer / downconverter.

It’s all Software Defined Radio, or “SDR”. There are $20 USB dongles, but they lack the frequency range and bandwidth I’m talking about.

Regards,

– Alan [SA-Penguin]

15

The dongles typically do 60MHz-1700MHz--I doubt that you'll do better
by hooking an ADC to the BBB. The dongles do it by having a front-end
tuner and specialized signal processor.