The SCLK mode is wrong, it should be an input.
Changing SCLK to an input works.
Thank You
Isn’t that the serial clock? Isn’t it generated by the host and thus an output? Or is it generated by some hardware and taking it over as an output is clobbering that?
Ok at least I’m not that stupid then. 
Your are totally right but I didn’t find any reference explaining that.
In the manual from TI,
AM335x ARM® Cortex™-A8 Microprocessors(MPUs)
Technical Reference Manual - SPRUH73H
Session 24.2.3: McSPI pin list there is a description about SPIx_SCLK and you read:
SPI serial clock (output when master, input when slave)
There is also one note at the bottom saying:
(1)This output signal is also used as a re-timing input. The associated CONF___RXACTIVE bit for the output clock
must be set to 1 to enable the clock input back to the module.
Thank you for the tip.
Thanks - you saved my day! I just ran into the same quirk. Truly bizzare that the SPI_CLK pinmux has to be set as an input in master mode where the pin is clearly an output.
It’s probably for clock-stretching. Both pins clock and data need to go both ways.
I2C uses clock stretching but I’m not aware of any SPI interfaces that do it. However, it may be that the hardware is shared.
OK sorry I thought you were referring to config pin on I2C.
I2C uses clock stretching but I’m not aware of any SPI interfaces that do it. However, it may be that the hardware is shared.