Hi. I'm Harikrishnan, a final year undergrad student from BITS Pilani Goa campus. I have experience working with low level embedded software. I was the engineering lead of Hyperloop India, one of the 24 teams that built and tested their pods at the 2017 SpaceX Hyperloop pod design competition. I was introduced to Beaglebone by Vaibhav Choudhary, a former Beagleboard GSoCer and member of the Hyperloop India team. I was impressed by its features, and decided to use it for handling interactions between the pod's CAN bus and the external network.
I also have experience working with low level embedded software. I have ported FreeRTOS to revision 1.9.1 of the RISC-V ISA (https://github.com/illustris/FreeRTOS-RISCV), to verify the correctness of a 5 stage in-order RISC-V processor I helped design (https://bitbucket.org/casl/shakti_public).
I'm interested in working on the PRU DMA project as part of GSoC 2018. But while reading up on the topic, I came across this project from GSoC 2017 : https://gist.github.com/maciejjo/58a0d0213712e67fba9d0061f6b5bead
It's not entirely clear what additions are expected to last year's work this year. Can someone please clarify?