I have a Beaglebone Black running the last Debian image and for my current project I need to cross-compile it with Eclipse from my WIndows OS.
I’m fairly new both to microcontrollers and C++ (programming in general if I am to be honest) and right now I’m still trying to understand if my assignment is doable!
Here it goes:
I need to sample with the built-in ADC of the BBB an analog input, count the samples and find a way to ‘force’ the ADC-clock rollover to synchronize with an external clock
Do you think this is feasible? I haven’t find, strangely enough, anything online about the last two, I’m googling the wrong way?
The FSM module in the TSC_ADC_SS can either get triggered by software or by an external hardware event (TIMER4-7 or PRU_ICSS pr1_host_intr0). See SRM chapter 12 for details.
The best way how to synchronize with an external clock depends on the clock frequency and the timming accuracy requirements. For high accuracy or above ~10 KHz you may need customized software.
But below that frequency you may be happy with a simple solution: The ADC operates at a fast sampling rate and the host CPU just reads the current value when the external clock fires. This is feasible with libpruio. (You may see some latency when the host CPU is busy by any system interrupt.)
BR
BTW: Cross-compiling adds further problems. Why not compiling on the BBB?
Once you install it, open eclipse and try to compile the hello world program; once that works step 2
step 2.
While I highly recommend the book (id get it make your life much easier); goto http://exploringbeaglebone.com/chapter1/ and read it till your reach the ADC bit; there is a github for the book, which has adc examples.;
the book explains how to configure the adc, and so do a lot of website; recommend you search google for “uenv.txt+BB-ADC”
Hi TJF, thanks for your reply!
I was hoping not to have to resort to use PRUs D: , for now the low accuracy given by the ADC clock will have to do. (btw why 10 kHz accuracy? it’s caused by Linux non-real-time-ness? Otherwise ADC clock frequency should be 1,6 MHz max right?)
Other random question: I suppose that if I sync the BBB system clock to an external clock the ADC’s one won’t be affected by it right? I mean they have different time ‘domain’.
Corss-compiling I’ll be able to debug my procject.
Host CPU and TSC_ADC_SS have different clock domains. Internal ADC clock rate is 24 MHz. The theoretical maximum sample rate is 1.6 Msamples/s (= 15 cycles@24MHz in single shot mode) or 1.74 Msamples/s (= 14 cycles in continous mode). In praxis it’s 200 ksamples/s.
The PRUSS are first choise for real time tasks with high timing accuracy.
Below 10 ksamples/s the CPU latency (due to Linux non-real-time-ness) is small (less than 10 % on a vanilla system).
When you need concrete hints, you’ll have to specify your timing requirements:
Is the external clock a regular pulse train?
What frequency?
Which maximum latency is required between clock pulse and ADC sample?
BR
Good evening!
thanks for the conciseness (btw with Host CPU you mean the bbb one?)!
You are fairly right about the lack of requirements in my question, the main problem is that I don’t really have one! The lower the latency the better could be the tagline of my project.
The original plan was to use as synchronization source (of the system clock) a ptp clock or ntp server and acquire the samples one second (200ksamples) a time and attach a timetag to every one of them, and thatìs why I was looking for a way to force the fifo counter rollover, I’ve the horrible feeling to have posed the question the wrong way and have mistaken the whole clock concept.
It’s still not at all clear to me how the system wall time and the adc sample time could be related, here another question similar to the one I have, Rick M suggests to:
use a sw PLL with a frequency related to the needed accuracy, linked to the pps generated by a GPS module, to update a timer.
let the PRU read the timer value at every sample
subtract the reading latencies
the problem is that I don’t have a PPS signal avaiable, I could modify the ntpd poll interval of the ntpd. It would be perfect if I could enable the PRU IEP timer (ocp_clk 200 Mhz) )soon after the gettimeoftheday() function call and then trigger the ADC.
Is this nonsense talk?
Connect your external clock and let the PRU watch a GPIO pin or an analog input and start the measurement on a certain state. Check out the triggers example.
I don’t have an external clock that I can use a trigger…!
I cant say, unless you specify your requirements.
I need to timetag the samples with an accuracy in the order of us (or less if possible) referred to the system clock previously synchronized with ntp.
In a very semplified way you suggest that I have to:
use libruio to start the measurement and read the system clock using one PRU
use the other PRU to increase ADC sample freq
?
I’ll probably need to read more about scratchpad register and XIN XOUT and all the functionality in libruio.
but first I should loose my specs in order to make things easier, lets say that ms accuracy is acceptable, should it be possible to avoid using PRUS?