Hello,
I’ve been working to create an industrial temperature derivative of the BBB(BeagleBoneBlack). In doing so I’ve noticed that the DDR3 SDRAM part numbers that are used are DDR3L or 1.35V parts. However, the design uses the TPS65217C device which automatically sets the DDR3 voltage to 1.5 volts upon power up. After going through the Uboot source, I found that software does not change the DCDC1 from it’s default value of 1.5V.
I believe the datasheet for the Micron part says that even though it supports DDR3L 1.35V mode, it can also run at 1.5V range and will be in DDR3 mode.
Was this by design? Mostly I’m just looking for a “Yep, we meant to do that and it’s A-OK”
SW is supposed to set it to 1.35V. Sounds like it got dropped somewhere because initially it did… It was designed this way because when it was designed, the PMIC defaulted to 1.5V. Since the design there is a TPS65217D that was release later that supports the 1.35V initial setting.
Yep, I meant to do that and Yes it is OK, however I prefer the SW folks fix UBoot, if it isn’t too much trouble.
269 /*
270 * Increase USB current limit to 1300mA or 1800mA and set
271 * the MPU voltage controller as needed.
272 */
273 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
274 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
275 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
276 } else {
277 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
278 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
279 }
But that only happens if you have the "beaglebone black" header in eeprom:
262 /*
263 * Override what we have detected since we know if we have
264 * a Beaglebone Black it supports 1GHz.
265 */
266 if (board_is_bone_lt(&header))
Ahh. Correct so that needs to be added to the EEPROM to work or a custom UBoot created for non conforming boards, those without EEPROM or EEPROM with different information in the EEPROM.
Note that the question was about DCDC1 and DDR voltage not DCDC2/3 (CORE and MPU) voltage. I don’t know what initial bring-up U-Boot was whacking DCDC1 but it never reached the rest of the world so it’s more a happy accident that should be corrected (and wouldn’t be too hard to do, if anyone out there is looking for a reason to get their feet wet ).
SW is supposed to set it to 1.35V. Sounds like it got dropped somewhere
because initially it did… It was designed this way because when it was
designed, the PMIC defaulted to 1.5V. Since the design there is a TPS65217D
that was release later that supports the 1.35V initial setting.
269 /*
270 * Increase USB current limit to 1300mA or 1800mA and set
271 * the MPU voltage controller as needed.
272 */
273 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
274 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
275 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
276 } else {
277 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
278 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
279 }
But that only happens if you have the “beaglebone black” header in eeprom:
262 /*
263 * Override what we have detected since we know if we have
264 * a Beaglebone Black it supports 1GHz.
265 */
266 if (board_is_bone_lt(&header))
So you’ll have to override that check.
Note that the question was about DCDC1 and DDR voltage not DCDC2/3 (CORE and MPU) voltage. I don’t know what initial bring-up U-Boot was whacking DCDC1 but it never reached the rest of the world so it’s more a happy accident that should be corrected (and wouldn’t be too hard to do, if anyone out there is looking for a reason to get their feet wet ).
Yeah, I was looking for DCDC1 and couldn’t find it, so I’m working on adding it now. Not sure how quick I’ll get it posted, so I wouldn’t mind someone else chiming in with the fix.
SW is supposed to set it to 1.35V. Sounds like it got dropped somewhere
because initially it did… It was designed this way because when it was
designed, the PMIC defaulted to 1.5V. Since the design there is a
TPS65217D
that was release later that supports the 1.35V initial setting.
269 /*
270 * Increase USB current limit to 1300mA or 1800mA and
set
271 * the MPU voltage controller as needed.
272 */
273 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
274 usb_cur_lim =
TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
275 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
276 } else {
277 usb_cur_lim =
TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
278 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
279 }
But that only happens if you have the “beaglebone black” header in eeprom:
262 /*
263 * Override what we have detected since we know if we
have
264 * a Beaglebone Black it supports 1GHz.
265 */
266 if (board_is_bone_lt(&header))
So you’ll have to override that check.
Note that the question was about DCDC1 and DDR voltage not DCDC2/3 (CORE and
MPU) voltage. I don’t know what initial bring-up U-Boot was whacking DCDC1
but it never reached the rest of the world so it’s more a happy accident
that should be corrected (and wouldn’t be too hard to do, if anyone out
there is looking for a reason to get their feet wet ).
Well, the original v2013.04 patchset can be seen here:
I don’t have my tps decoder ring, so i’m not sure if that address is
more then just the usb current setting…
I believe the equivalent hack to set DCDC1 to 1.35V is
+/* 0x24 is the address of the PMIC /
+/ 0x0b is the password register /
+/ 0x0e is the DEFDCDC1 register /
+/ 0x73 is the password (register 0x0e ^ 0x7d) /
+/ 0x12 sets the DCDC1 to 1.35V /
+/ Sequence must be repeated twice for password protection */ #define CONFIG_BOOTCOMMAND \
"i2c mw 0x24 0x0b 0x73; " \
"i2c mw 0x24 0x0e 0x12; " \
"i2c mw 0x24 0x0b 0x73; " \
"i2c mw 0x24 0x0e 0x12; " \
I’m just about to try this out, but don’t mind if someone beats me to it.
>>
>> > SW is supposed to set it to 1.35V. Sounds like it got dropped
>> > somewhere
>> > because initially it did.. It was designed this way because when
it
>> > was
>> > designed, the PMIC defaulted to 1.5V. Since the design there is a
>> > TPS65217D
>> > that was release later that supports the 1.35V initial setting.
>>
>> It should be set here:
>>
>>
>>
>> board/ti/am335x/board.c · master · U-Boot / U-Boot · GitLab
e6021a21e71d7d0f5c840b793ce7fdf98fae;hb=HEAD#l275
>>
>> 269 /*
>> 270 * Increase USB current limit to 1300mA or
1800mA
>> and
>> set
>> 271 * the MPU voltage controller as needed.
>> 272 */
>> 273 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
>> 274 usb_cur_lim =
>> TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
>> 275 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
>> 276 } else {
>> 277 usb_cur_lim =
>> TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
>> 278 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
>> 279 }
>>
>>
>> But that only happens if you have the "beaglebone black" header in
>> eeprom:
>>
>> 262 /*
>> 263 * Override what we have detected since we know
if
>> we
>> have
>> 264 * a Beaglebone Black it supports 1GHz.
>> 265 */
>> 266 if (board_is_bone_lt(&header))
>>
>> So you'll have to override that check.
>
>
> Note that the question was about DCDC1 and DDR voltage not DCDC2/3
(CORE
> and
> MPU) voltage. I don't know what initial bring-up U-Boot was whacking
> DCDC1
> but it never reached the rest of the world so it's more a happy
accident
> that should be corrected (and wouldn't be too hard to do, if anyone
out
> there is looking for a reason to get their feet wet ).
Well, the original v2013.04 patchset can be seen here:
SW is supposed to set it to 1.35V. Sounds like it got dropped
somewhere
because initially it did… It was designed this way because when it
was
designed, the PMIC defaulted to 1.5V. Since the design there is a
TPS65217D
that was release later that supports the 1.35V initial setting.
269 /*
270 * Increase USB current limit to 1300mA or 1800mA
and
set
271 * the MPU voltage controller as needed.
272 */
273 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
274 usb_cur_lim =
TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
275 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
276 } else {
277 usb_cur_lim =
TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
278 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
279 }
But that only happens if you have the “beaglebone black” header in
eeprom:
262 /*
263 * Override what we have detected since we know if
we
have
264 * a Beaglebone Black it supports 1GHz.
265 */
266 if (board_is_bone_lt(&header))
So you’ll have to override that check.
Note that the question was about DCDC1 and DDR voltage not DCDC2/3 (CORE
and
MPU) voltage. I don’t know what initial bring-up U-Boot was whacking
DCDC1
but it never reached the rest of the world so it’s more a happy accident
that should be corrected (and wouldn’t be too hard to do, if anyone out
there is looking for a reason to get their feet wet ).
Well, the original v2013.04 patchset can be seen here:
I don’t have my tps decoder ring, so i’m not sure if that address is
more then just the usb current setting…
I believe the equivalent hack to set DCDC1 to 1.35V is
+/* 0x24 is the address of the PMIC /
+/ 0x0b is the password register /
+/ 0x0e is the DEFDCDC1 register /
+/ 0x73 is the password (register 0x0e ^ 0x7d) /
+/ 0x12 sets the DCDC1 to 1.35V /
+/ Sequence must be repeated twice for password protection */ #define CONFIG_BOOTCOMMAND \
"i2c mw 0x24 0x0b 0x73; " \
"i2c mw 0x24 0x0e 0x12; " \
"i2c mw 0x24 0x0b 0x73; " \
"i2c mw 0x24 0x0e 0x12; " \
So I got this to work via this sequence in the terminal…
