What is the fastest interface provided between the BeagleBone and the
Cape? I know there are a few serial interfaces like async serial and
SPI, but are there any high speed interfaces defined, perhaps
something with parallel I/O supported by DMA?
Rick
Well, you have the MMC which is 49MB/S. You have the GPMC which is 16b wide @ 100MHZ, so that is roughky 200MB/s. Both have access to DMA.
Gerald
Gerald, related to that, are the traces for MMC and GPMC length
matched from the SoC to the headers on the Bone?
Sorry if this has been asked and answered before.
-Andrew
No, they are not matched lengths. So, you will need to compensate for that.
Gerald
Thanks for the reply.
Is the MMC interface used by the SD socket on the BB? I assume using
the GPMC would not interfere with anything else (not sure what GPMC
is, but I expect the GP is "general purpose", no?) Is the GPMC used
by any other capes currently? I assume if I dig in the user guide for
the CPU chip I will find timing info on the interface? Hopefully
matched lengths won't be required. I expect it can be slowed down if
needed.
How is the GPMC supported in software? I think 200 MB/s is plenty of
speed for anything I would want to do assuming it could actually be
supported in the software. I expect continuous operation at 200 MB/s
would not be possible, but any idea of what is a practical max to/from
memory? Getting it into memory would be the responsibility of the
cape board, anything beyond that would be up to the application.
Rick
See below.
Gerald
Thanks for the reply.
Is the MMC interface used by the SD socket on the BB?
It uses one of them.
I assume using
the GPMC would not interfere with anything else (not sure what GPMC
is, but I expect the GP is “general purpose”, no?)
GPMC…General Purpose Memory Controller…Address, data, control signals.
Is the GPMC used
by any other capes currently?
It does not matter. Cape alignment is something that can’t be controlled. Too big of a task. Besides, each pin can have up to 7 functions on it, so these pins can be all sorts of signals. You can look at the System Reference Manual for more information.
I assume if I dig in the user guide for
the CPU chip I will find timing info on the interface?
Yes. Look at the SRM first to see th epins on the expansion headers.
Hopefully
matched lengths won’t be required. I expect it can be slowed down if
needed.
It can be, but if you do a PCB, matched lengths is not that big of a deal.
How is the GPMC supported in software?
Should be, It maps as memory to the processor, just read and write to the address. You have to set up the pin muxing.
I think 200 MB/s is plenty of
speed for anything I would want to do assuming it could actually be
supported in the software. I expect continuous operation at 200 MB/s
would not be possible, but any idea of what is a practical max to/from
memory?
Well, you have DMA that can be used to read it into DDR. Of course if that is faster than the SW can operate on it, it may not be needed.
Getting it into memory would be the responsibility of the
cape board, anything beyond that would be up to the application.
Just map whatever it is as memory and the DMA will do the rest.
Thanks for your responses. See below.
Rick
See below.
Gerald
> Thanks for the reply.
> Is the MMC interface used by the SD socket on the BB?
It uses one of them.
So is there an MMC interface on the cape connectors that is not used
by the internal circuitry on the BB? Sharing an interface is a lot
harder than using a dedicated interface.
> I assume using
> the GPMC would not interfere with anything else (not sure what GPMC
> is, but I expect the GP is "general purpose", no?)GPMC..General Purpose Memory Controller..Address, data, control signals.
I assume the DDR memory has it's own interface separate from the
GPMC? Or is it easily shared? A 200 MHz interface can create a lot
of issues if there is are multiple drivers, especially going off
board.
> Is the GPMC used
> by any other capes currently?It does not matter. Cape alignment is something that can't be controlled.
Too big of a task. Besides, each pin can have up to 7 functions on it, so
these pins can be all sorts of signals. You can look at the System
Reference Manual for more information.
It may not matter to you, but I see no reason to walk into a wall if
I can see it in my way. I may decide to continue use the interface
anyway, but I would like to know if any of the current capes use this
interface. If you don't know, that's fine.
Is there any sort of guide to the expansion bus usage by the various
capes?
> I assume if I dig in the user guide for
> the CPU chip I will find timing info on the interface?Yes. Look at the SRM first to see th epins on the expansion headers.
> Hopefully
> matched lengths won't be required. I expect it can be slowed down if
> needed.It can be, but if you do a PCB, matched lengths is not that big of a deal.
Only if I am not aiming at a moving target. I don't have control over
the BB layout unless I decide to manufacture the BB as well. So for
now I would prefer to avoid dealing with matching lengths if that is
not a design spec on the BB. Or are you saying that the BB has
matched lengths for this interface going to the connector?
> How is the GPMC supported in software?
Should be, It maps as memory to the processor, just read and write to the
address. You have to set up the pin muxing.
Ok, memory mapped I/O is great. I can implement a virtual FIFO on my
side.
> I think 200 MB/s is plenty of
> speed for anything I would want to do assuming it could actually be
> supported in the software. I expect continuous operation at 200 MB/s
> would not be possible, but any idea of what is a practical max to/from
> memory?Well, you have DMA that can be used to read it into DDR. Of course if that
is faster than the SW can operate on it, it may not be needed.
High burst speeds are never a problem and can reduce latencies. If
there a bottlenecks elsewhere that is not the concern here. Best that
the bottleneck is not the interface.
See below.
Gerald
Thanks for your responses. See below.
Rick
See below.
Gerald
Thanks for the reply.
Is the MMC interface used by the SD socket on the BB?
It uses one of them.
So is there an MMC interface on the cape connectors that is not used
by the internal circuitry on the BB? Sharing an interface is a lot
harder than using a dedicated interface.
YES, on the expansion headers. There is no access available for the one used on the main board.
I assume using
the GPMC would not interfere with anything else (not sure what GPMC
is, but I expect the GP is “general purpose”, no?)GPMC…General Purpose Memory Controller…Address, data, control signals.
I assume the DDR memory has it’s own interface separate from the
GPMC? Or is it easily shared?
Yes. DDR has a totally seperate bus…
A 200 MHz interface can create a lot
of issues if there is are multiple drivers, especially going off
board.
That is your call as you will be the only one using it. It is all yours!
Is the GPMC used
by any other capes currently?It does not matter. Cape alignment is something that can’t be controlled.
Too big of a task. Besides, each pin can have up to 7 functions on it, so
these pins can be all sorts of signals. You can look at the System
Reference Manual for more information.It may not matter to you, but I see no reason to walk into a wall if
I can see it in my way.
That is the whole point. You can’t see it. There are Capes popping up all over the place. When you start your design, most likley 12 more will show up before you finish it. You will never beable to finish it based on the capses that keep coming. Thi sexapnsion bus i snot like PCI or a stnadard bus. There are way to many options on each pin to crreate any sort of a standard.
I may decide to continue use the interface
anyway, but I would like to know if any of the current capes use this
interface.
No they don’t currently but they do use the pins. And htere is one abpout to start that will use thhe GPMC pins.
If you don’t know, that’s fine.
Is there any sort of guide to the expansion bus usage by the various
capes?
No. There is a EEPROM that comes with each Cape to say how each pin is being used and if they choose, there is a WIKI that shows what pins are used and how they are used. There will be no guide written that restricts the numbers of Capes nor what they do. As I said, Cape interoperability is not something that can be managed. With 7 different functions on each Pin, it just is too big to handle. Take a look at the SRM and see what different signals are present on each pin to get an idea as to what I am trying to say.
I assume if I dig in the user guide for
the CPU chip I will find timing info on the interface?Yes. Look at the SRM first to see th epins on the expansion headers.
Hopefully
matched lengths won’t be required. I expect it can be slowed down if
needed.It can be, but if you do a PCB, matched lengths is not that big of a deal.
Only if I am not aiming at a moving target. I don’t have control over
the BB layout unless I decide to manufacture the BB as well.
Well, I do. There will be no changes in the lengths of these signals.
So for
now I would prefer to avoid dealing with matching lengths if that is
not a design spec on the BB. Or are you saying that the BB has
matched lengths for this interface going to the connector?
I am saying they do not have matched lengths. There was not enough space on the board to wiggle the lines to make them all line up.
How is the GPMC supported in software?
Should be, It maps as memory to the processor, just read and write to the
address. You have to set up the pin muxing.Ok, memory mapped I/O is great. I can implement a virtual FIFO on my
side.
Correct.