Beaglebone PRU - GPIO and ADC

Hi Jason,

I am about to embark on some PRU GPIO coding for a small project I have in mind. I have been trying to watch as much of your YouTube seminars of the Christmas Break as I can.

I have been looking at your presentation slides and am puzzled with Slide 25 “PRU low-latency I/Os”. I notice that a couple of the pins are suffixed with ‘PRU1_16 in’ and 'PRU0_15 out 11 ---- 12 PRU0_14 out ’

What is the significance of the in and out?

Can the other GPIO pins be accessed by the PRU?

Also can you point me at any examples which use the Analogue Inputs in the PRU ?

I’m not Jason. I’ll answer, though.

I have been looking at your presentation slides and am puzzled with Slide 25 “PRU low-latency I/Os”. I notice that a couple of the pins are suffixed with ‘PRU1_16 in’ and 'PRU0_15 out 11 ---- 12 PRU0_14 out ’

What is the significance of the in and out?

Can the other GPIO pins be accessed by the PRU?

A GPIO operates in a direction, either output or input. It’s possible to change the direction at run-time.

All GPIO subsystems can get controlled over the OCP master port (2-3 PRU cycles latency).

Low latency GPIO can get controlled directly by the PRUSS at 100 MHz. Maximum 14 header pins are available on PRUSS-0 (when HDMI is disabled).

Also can you point me at any examples which use the Analogue Inputs in the PRU ?

Find examples in the source code of libpruio.

BR

I'm not Jason. I'll answer, though.

I have been looking at your presentation slides and am puzzled with Slide 25

"PRU low-latency I/Os". I notice that a couple of the pins are suffixed
with 'PRU1_16 in' and 'PRU0_15 out 11 ---- 12 PRU0_14 out '

What is the significance of the in and out?

In and out for the PRU pins indicates the direction of the signal. The
PRU direct I/O have unique buses for the input and output signals, so
(for instance) a pin that can function as a direct PRU output cannot
necessarily also function as a direct PRU input.

The pins are labeled with the PRU core they are connected to (PRU0 or
PRU1) and the register/direction they support (R31 = Inputs, R30 = outputs).

Can the other GPIO pins be accessed by the PRU?

A GPIO operates in a direction, either output or input. It's possible to
change the direction at run-time.

All GPIO subsystems can get controlled over the OCP master port (2-3 PRU
cycles latency).

There's significantly more overhead than 2-3 cycles. You only see 2-3
cycles of latency for the first few posted writes. Sustained writes or
any reads have significantly longer latencies:

https://github.com/machinekit/machinekit/blob/master/src/hal/drivers/hal_pru_generic/pru_generic.p#L135-L163