Beagley-ai spi0 pin clarification

On the pinout it shows 2 spi0 cs0. I read the * and need to know what is the correct pin to be BB compatible?
spi

Currently, these overlays, are mirroring the same spi pins that RPI uses for spidev0…

k3-am67a-beagley-ai-spidev0.dts
k3-am67a-beagley-ai-spi0-1cs.dts
k3-am67a-beagley-ai-spi0-2cs.dts

SPI0 pins are GPIO 7, 8, 9, 10, 11

Regards,

The overlay looks like bit-bang in software, I going have an adc on that feeding the dsp and would like the max bandwidth from native. Not sure why the RTC chip is commented out, is that used for the hardware spi? Assuming this is done for RPI compatibility, I don’t need that. Are the soc balls for hardware spi connected to the header?

	sck-gpios = <&mcu_gpio0 2 GPIO_ACTIVE_HIGH>;
	miso-gpios = <&mcu_gpio0 4 GPIO_ACTIVE_HIGH>;
	mosi-gpios = <&mcu_gpio0 3 GPIO_ACTIVE_HIGH>;

	num-chipselects = <1>;
	cs-gpios = <
		&mcu_gpio0 0 GPIO_ACTIVE_HIGH
	>;

	status = "okay";

//	mcp795@0 {
//		compatible = "maxim,mcp795";
//		reg = <0x0>;
//		spi-max-frequency = <100000>;
//	};
};

Correct it’s bit-banged for RPI compatibility on those pins only…

Left over from testing, i can remove that…

MCU_SPI0 and SPI2 are the most complete.

MCU_SPI0:

hat_19:MCU_SPI0:B12:MCU_SPI0_D0:0::
hat_21:MCU_SPI0:C11:MCU_SPI0_D1:0::
hat_23:MCU_SPI0:A9:MCU_SPI0_CLK:0::
hat_24:MCU_SPI0:C12:MCU_SPI0_CS0:0::
hat_26:MCU_SPI0:B3:MCU_SPI0_CS2:2::

SPI2

hat_08:SPI2:F24:SPI2_CLK:1::
hat_11:SPI2:A26:SPI2_D1:1::
hat_12:SPI2:D25:SPI2_CS1:1::
hat_35:SPI2:C26:SPI2_CS3:1::
hat_36:SPI2:A25:SPI2_D0:1::
hat_40:SPI2:B25:SPI2_CS2:1::

Regards,

1 Like

Thank you for clearing that up.