BeagleY-AI still no AI working?

Hi, after few days working on this cute little board, I love TI and BeagleBoard’s product quality.

I want to run TI J722SXH01EVM SDK AI examples on BeagleY-AI, now I can build uboot and boot on TI SDK’s yocto image, build examples etc. And now board boot directly into demo page.

But all examples involve DSP part crashes:
Failed to initialize DMA HEAP [/dev/dma_heap/carveout_vision_apps_shared-memories

I guess I have to diff Linux DTC to figure out if DSP part is not initialized, but I want to know:
Do BeagleBoard has an official plan to port these demo programs? or, at least provide a working kernel with DSP, PLEASE. If not so, it defeats the whole purpose of naming it “BeagleY-AI”.

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You might have to work on the dtb, it will not be the same for evm and y board. Look that over, they do have some shared memory carved out and that would be a very critical point. Might be cheaper to just get the evm and work off of it. Some of this stuff is really cool, cool if you have endless resources to support the ongoing dev.

My guess is DSP memory space address is hard coded in TI’s bin files, if DDR4 size<8GB then they will never be initialized.

I had quite few hours looking at the DT source, no time with kernel bindings yet.

If my guess is right I will rework my board to 8G.

Hi @tty0x24 , do you have a yocto image for BeagleY-AI ?

Hi mls, yocto image from TI SDK doesn’t run on BeagleY-AI, SPL is incompatible.
I have dsp initialized:

root@BeagleBone:/opt/opt# cat /sys/class/remoteproc/remoteproc0/state 
running
root@BeagleBone:/opt/opt# k3conf dump processor
|--------------------------------------------------------------------------------|
| VERSION INFO                                                                   |
|--------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Wed Mar 27 21:29:14 UTC 2024)                |
| SoC    | J722S SR1.0                                                           |
| SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.0.6--w2023.01-j722s (Kool Koa)') |
|--------------------------------------------------------------------------------|

|------------------------------------------------------------------------------------------|
| Device ID | Processor ID | Processor Name       | Processor State  | Processor Frequency |
|------------------------------------------------------------------------------------------|
|   121     |       1      | WKUP_R5FSS0_CORE0    | DEVICE_STATE_ON  | 800000000           |
|     9     |       3      | MCU_R5FSS0_CORE0     | DEVICE_STATE_OFF | 800000000           |
|   262     |       4      | R5FSS0_CORE0         | DEVICE_STATE_OFF | 800000000           |
|   135     |      32      | A53SS0_CORE_0        | DEVICE_STATE_ON  | 1250000000          |
|   136     |      33      | A53SS0_CORE_1        | DEVICE_STATE_ON  | 1250000000          |
|   137     |      34      | A53SS0_CORE_2        | DEVICE_STATE_ON  | 1250000000          |
|   138     |      35      | A53SS0_CORE_3        | DEVICE_STATE_ON  | 1250000000          |
|   208     |      48      | C7X256V0_C7XV_CORE_0 | DEVICE_STATE_ON  | 1000000000          |
|   268     |      49      | C7X256V1_C7XV_CORE_0 | DEVICE_STATE_OFF | 1000000000          |
|   225     |     128      | HSM0                 | DEVICE_STATE_ON  | 500000000           |
|------------------------------------------------------------------------------------------|

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Thank you !
which image do you use ?

I built my image from scratch.

Unfortunately current work is not stable, to push a working build script on github require quite some time.

I believe next version from BB will resolve these issue, or it’s deliberately avoid DSP core working for consumers. I don’t want to spoil their intention.

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I had a fairly long response to this and decided to delete it. In a nutshell, if it smells it is rotten…

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Correct.

Try these bins if you want to use C7s with 4GB of DDR. You need to match the DTS in Linux as well but once you do the C7s spring to life. Then it’s a bit of dependency hell.

Also may or may not have reworked 2 boards with 8GB DDR from Kingston… booting as of this morning. Nothing official just something fun I’m doing on the side to prove it’s possible.

My approach is from bottom to up.

I have built TVM from scratch on x64 and now trying to cross build for J722S. Right now the TIDL part interests me more and I need to close this job before trying else things. It’s very glad to see you had your edgeai part up and running. I will spend my time by following your steps, thanks for the upload.

Do you ever want to put a v3 link camera on a drone? Since you have image processing backend up and running, a rpi camera with existing DT layers might be a good starting point.

I can share some news, that AI is working on BeagleY-AI, except some caveats not related to EdgeAI itself. Here is the video about. Sorry it is not in English language but there are broken subtitles:

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I put short notes about my changes on the GitLab, you can check here:

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Thanks for extracing dtc and combining it to ti’s uboot branch. I will rebuild my image with the project you provided. Right now I and another forum member are about to be able to compile model with TVM, but we are stuck on the RAM size settings with TVM build. If you are interesting joining in, please PM your email we can work together.

I need to add some explanation to my previous post.
In the Git repository that I shared, there are three parts: u-boot, updates, Linux DT updates and TI PSDK updates.
All changes I did are related to changing memory layout and boot loader changes to make TI PSDK image booting on BeagleY-AI.
TI equipped its AM67A EVM board with 8GB of DDR memory, but BeagleY-AI has only 4GB of DDR memory. Other thing, in their PSDK TI made emphasis on using of, what is called, “high memory”. It is memory located beyond 32bit addressing range. It is not necessary but it is done. For example, in TI PSDK high_ddr_shared_memory starts at 0x9,0000,0000 address which does not exist for BeagleY-AI.
In my changes I reintroduced memory layout similar to one used in J721E boards like sk-j721e and Beaglebone AI-64. I replaced high_ddr_shared_memory with ddr_shared_memory with physical address 0xc000,0000. These changes are implemented in Python script gen_linker_mem_map.py which generates DT dtsi file used as a template for Linux DT file, .h memory layout and .cmd linker scripts for all DSPs/CPUs. This was one part. Other part is about memory access permissions. These are implemented very different way comparing with other TDA4 PSDK parts, the same j721e, for example. All memory regions are defined in *.syscfg files. I had to add one more for MCU2_0, it was not there by some reason, because it was crashing on some cache operations in my case.

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