Blinky Verilog demo issues

Followed the Customize Gateware using Verilog demo and encountered some issues. I called my gateware TEST_CAPE, but otherwise followed the demo. Used the Beagleboard Gitlab build system and it seemed to build correctly.
However, when it booted it reported:
[1.730046] Design Info:
Design Version: 02.16.1
[1.740462] Attempting to select eMMC … Failed

later in the boot I got:
[ 3.623722] Waiting for root device /dev/mmcblk0p3…
[ 3.745685] mmc0: error -110 whilst initialising MMC card
[ 4.013311] mmc0: error -110 whilst initialising MMC card
[ 4.296233] mmc0: error -110 whilst initialising MMC card
[ 4.625548] mmc0: error -110 whilst initialising MMC card

at which point it stopped and I figured it was soft bricked.
However, after a couple of restart attempts it did boot.
However, listing the device tree, it showed VERILOG_TEMPLATE as the device tree name rather than TEST_CAPE.
So why are MY_CUSTOM_FPGA_DESIGN and VERILOG_TEMPLATE showing up rather than TEST_CAPE and why is it having issues booting?

Also, the instructions do not say if the dtso file needs a particular name so I’m not sure if that is part of the problem.

The LED did correctly blink, so the code did actually load into the FPGA.

Do not forget to set CAPE_OPTION to point at your cape design in custom-fpga-design/my_custom_fpga_design.yaml. In your case this should be CAPE_OPTION:TEST_CAPE.
There is no need for a specific dtso file name. Only that there is one (if required) and that it has the file extension .dtso.
I see the same boot issue. I will dig into it.

Thank you. I did have that properly set.

Incidentally, can the yaml file be renamed so the bit-stream file ends up reflecting the name of my project, or must it be “my_custom_fpga_design.yaml”?

Yes, should be possible.