Bone and TPS65217 SLEEP state

I'm attempting to put the Bone into SLEEP state, as defined by the
TPS65217, where only LDO1 stays active but all other power rails turn
off. I want to do this so I can keep the real time clock running in
the AM335x but not consume much power.

I am not trying to do any kind of suspend to ram or hibernation.

The default setting for the TPS65217 STATUS REGISTER (register 0x0A)
bit 7 is "0" which should put the TPS65217 into SLEEP mode when PWR_EN
(same net as PMIC_POWER_EN from the AM335x) is pulled low.

I pull the PMIC_POWER_EN pin low by causing an ALARM2 condition within
the AM335x real time clock module. When I set the TPS65217 STATUS
REGISTER bit 7 to "1" and then pull PMIC_POWER_EN low, I can
successfully enter OFF mode. Exiting OFF mode (ie: powering up) is
accomplished by inserting either USB or AC power while maintaining
input power to the TPS65217 (either by using the other one than I'm
plugging, or via lithium battery on P6) or by pushing the power button
(on P9). But unless I perform one of these actions, the TPS65217 stays
OFF, rather successfully. But OFF mode disables LDO1 meaning my real
time clock forgets what time it is, thus, I want to use SLEEP mode.

But, when I attempt to enter SLEEP mode, I'm able to enter it, but then
the TPS65217 powers right back up. I'm seeing the PMIC_POWER_EN line
from the AM335x going low because of the ALARM2, but then 60 ms later,
it goes high again. I assume this is because the PMIC_POWER_EN I/O
goes to high-z pulled-up state while in reset (the data sheet doesn't
say what the state of pins are when the AM335x is off, just during
and post-reset, so I assume powered off state is the same as reset
state).

There's no pull-down on the PMIC_POWER_EN line to counteract the weak
pull-up that is internal to the AM335x (at least during reset, but
probably during power off, too). Possibly having a pull-down here would
cause the Bone to never power up under some circumstances, but I've not
attempted to rework one this way, yet.

In OFF mode, the TPS65217 won't wake except for power button or the
rising edge of a power source. But in SLEEP mode, the TPS65217 will
wake because of PWR_EN going high or any of the conditions to wake from
OFF mode. Because of this, I'd like PMIC_POWER_EN to stay low unless
being driven by the AM335x to be high.

Is this possible? Or am I most likely doing something else wrong? Am
I forgetting a register setting in the TPS65217?

Has any one had success getting the TPS65217 to enter SLEEP mode on the
Bone?

Thanks,
Andrew

The reason I'm even able to wake at all from OFF state by inserting the
AC power adapter is _BECAUSE_ PMIC_POWER_EN is already high...
Otherwise, if PWR_EN was low, the only way to wake is USB power
insertion or power button, neither of which I want.

hmmm.

So maybe it's not possible to do what I want, which is to keep LDO1 on
and wake from SLEEP upon AC power insertion. That sucks. I guess cape
will get a real time clock on i2c, then...

-Andrew

PS: Thanks list for listening to my problem :slight_smile: Have a good Olympics.

The default setting for the TPS65217 STATUS REGISTER (register 0x0A)
bit 7 is "0" which should put the TPS65217 into SLEEP mode when
PWR_EN (same net as PMIC_POWER_EN from the AM335x) is pulled low.

I pull the PMIC_POWER_EN pin low by causing an ALARM2 condition
within the AM335x real time clock module. When I set the TPS65217
STATUS REGISTER bit 7 to "1" and then pull PMIC_POWER_EN low, I can
successfully enter OFF mode. Exiting OFF mode (ie: powering up) is
accomplished by inserting either USB or AC power while maintaining
input power to the TPS65217 (either by using the other one than I'm
plugging, or via lithium battery on P6) or by pushing the power
button (on P9). But unless I perform one of these actions, the
TPS65217 stays OFF, rather successfully. But OFF mode disables LDO1
meaning my real time clock forgets what time it is, thus, I want to
use SLEEP mode.

But, when I attempt to enter SLEEP mode, I'm able to enter it, but
then the TPS65217 powers right back up. I'm seeing the
PMIC_POWER_EN line from the AM335x going low because of the ALARM2,
but then 60 ms later, it goes high again. I assume this is because
the PMIC_POWER_EN I/O goes to high-z pulled-up state while in reset
(the data sheet doesn't say what the state of pins are when the
AM335x is off, just during and post-reset, so I assume powered off
state is the same as reset state).

See attached scope shot (hope it comes through). Tests on an A3 bone:
Ch1 is PMIC_PWR_EN.
Ch2 is VRTC (VLDO1)
Ch3 is RTC_PORz (LDO_PGOOD with resistor divider)

60 ms after PMIC_PWR_EN goes low, RTC_PORz starts falling. This will
reset the RTC IP block within the AM335x. The reset state for the
PMIC_PWR_EN pin is high. Thus, as soon as RTC_PORz is detected not-
high, the RTC resets (even though VRTC stayed up!) and pulls PMIC_PWR_EN
high again, enabling all the voltage rails on the TPS65217.

This is why I can't stay in SLEEP. The TPS65217 is declaring that an
LDO has fallen out of regulation (LDO2 has, it got turned off!) and thus
RTC_PORz is deasserted.

According to the TPS65217 data sheet, page 19, says:

* If the user disables a rail (either manually or through sequencer), it
has no effect on the PGOOD or LDO_PGOOD pin.

I read this to say, that if the TPS65217 is instructed to disable a
rail, PGOOD and LDO_PGOOD won't change state even if the rail its
monitoring is out of regulation.

Also, on page 19:

* If the user disables all rails (either manually or through sequencer)
PGOOD and/or LDO_PGOOD will be pulled low.

I'm not disabling "all rails," just all but LDO1. So LDO_PGOOD should
stay high.

Then, on page 20:

In normal operation LDO_PGOOD is high in ACTIVE and SLEEP state and low
in RESET or OFF state.

Which I read to say, if I go into SLEEP state, LDO_PGOOD should stay
high. It's not doing that for more than 60 ms...

There's no pull-down on the PMIC_POWER_EN line to counteract the weak
pull-up that is internal to the AM335x (at least during reset, but
probably during power off, too). Possibly having a pull-down here
would cause the Bone to never power up under some circumstances, but
I've not attempted to rework one this way, yet.

If there was a pull down on PMIC_POWER_EN, I believe the bone would
_NEVER_ power up. That's not really useful.

In OFF mode, the TPS65217 won't wake except for power button or the
rising edge of a power source. But in SLEEP mode, the TPS65217 will
wake because of PWR_EN going high or any of the conditions to wake
from OFF mode. Because of this, I'd like PMIC_POWER_EN to stay low
unless being driven by the AM335x to be high.

Is this possible? Or am I most likely doing something else wrong?
Am I forgetting a register setting in the TPS65217?

From u-boot, I'm able to write to the TPS65217 register 0x16
ENABLE_REGISTER to disable LDO2. When I do this, PGOOD_LDO stays high,
as expected.

From u-boot, I'm able to write to the TPS65217 register 0x1E
SEQUENCER_REGISTER_6 DEQDWN bit to initiate a power down (without
needing PMIC_PWR_EN to go low) and then I see SLEEP state voltage
levels, as I see above... VRTC stays up, PMIC_PWR_EN stays high (the
AM335x didn't pull it), but PMIC_PORz (LDO_PGOOD) goes low indicating
that either LDO1 or LDO2 is out of regulation.

This implies that LDO2 isn't under sequencer control during power down
and that LDO2 is going over current (the power LED draws more than 1 mA)
or either LDO1 or LDO2 have had a problem (which they haven't).

BUT! If I first disable LDO2 (turns the power LED off), then initiate a
power down, LDO_PGOOD _STILL_FALLS_!!! Which it shouldn't!

Guess I'll be visiting the e2e phorums... And calling my local rep...
And, populating R143 and depopulating R141 and R18. Which should then
set RTC_PORz to be controlled by the U17 gates based on an RC delay and
VRTC being up (LDO1). If that works, I'll let everyone know (I know
you're all on the edges of your seats!) :slight_smile:

-Andrew

SCRN0021.PNG

I give up. Sorry.

A5 and A6 bones don't populate quite a few of the components I need in
order to change over to using VRTC to set the RTC_PORz signal. The A3
did, but it's not worth my time to even try it.

I wasn't willing to test on A5 or A6 bones as I only have a small number
of them and most of them will be used for prototypes, soon. So I used
A3s (one died an inglorious death).

e2e doesn't have anything useful. I'm not willing to spend more time on
this, especially writing it all up for e2e since the responses there are
usually less than stellar. I'm pretty sure the TPS65217 is not doing
what its data sheet says, which isn't a first for TI parts in my
experience...

That the A3 bones use the TPS65217A (which is meant for the other AM335x
package) and the A5 & A6 use the TPS65217B might play into some of my
issues but...

XAM335x errata 1.0.5 says don't stop supplying VDD_CORE to pre-
production XAM3359 parts, or else the RTC will mess up the clock and not
count time correctly. Basically defeats the whole point of having the
SLEEP mode, all DC-DCs are off and just VRTC (LDO1) stays up, no one can
afford to keep VDD_CORE up just to keep a RTC alive when on battery!

So it seems as my desire and work is all for naught. Even if I got it
working, the XAM3359 will still screw it up. Hopefully production
AM335x parts will fix this, but I won't hold my breath.

Since even A6 bones appear to still be using preproduction XAM3359
parts, I'm done working on this. For good this time.

Cape will get a RTC and it'll run on a linear regulator off SYS voltage,
which, amazingly, actually stays present when the TPS65217 is in OFF
state and a battery is connected. On both A3 and A5 bones. Consistency
FTW! :slight_smile:

On a positive note, I did find that I don't need to play stupid RTC games
to set ALARM2 in order to power off, simply write to the TPS65217 SEQDWN
bit in the SEQ6 register. Horray! Simpler kernel board-file! :slight_smile:
I guess I'll take my small wins. I'll probably reply to that thread [1]
with a modified version of the latest patch.

[1]:https://groups.google.com/d/topic/beagleboard/K7DuusrJ6G4/discussion

-Andrew

Sorry. But ALL BeagleBones use TPS65217B. The early boards were programmed as TPS65217B using TPS65217A marked packages because the TPS65217B were not yet released. We have never built a BeagleBone with a TPS65217A device. It was programed at the factory as a TPS65217B.

The reset mode was changed to be generated by the TPS65217B instead of the external circuitry, That is why they are no longer populated.

Gerald

Ah, OK. Did not know about the A/B markings, assumed part identifiers
were correct. That makes sense.

Thanks!
-Andrew

Did u succeed in making the TPS65217 to enter sleep mode and to wake
it up? Do u have any updates on that?

This issue isn't the TPS65217, it's the AM335x. See the RTC clock
crossing errata on first gen silicon for AM335x. This issue should be
corrected in gen 2.0 and 2.1 silicon.

The BeagleBone Black or any BeagleBones built with rev 2.0 or 2.1
silicon shouldn't see this problem. I have not verified this.

On gen 1.0 silicon, don't use SLEEP state of TPS65217, it won't work.
Get an external RTC if you need RTC operation while in OFF mode.

-Andrew

Hello Andrew

Could you please point me to the documentation that describes the PMIC sleep? That is, you turn off the unnecessary power rails? I am working towards a low power application. I need to reduce the power consumption.

Secondly, can you give me some power consumption numbers that you got after you turned off the the PMIC power rails?

Thanks and Regards,
Abhijeet

It is in the PMIC datasheet.

http://www.ti.com/product/tps65217C

I cannot give you the power numbers. I don’t have them.

Gerald

<snip>

Secondly, can you give me some power consumption numbers that you got
after
you turned off the the PMIC power rails?

Search is your friend:
https://groups.google.com/d/msg/beagleboard/K7DuusrJ6G4/vEtB83u3vf0J
https://groups.google.com/d/msg/beagleboard/K7DuusrJ6G4/Jf4_y4_G0u4J

-Andrew