Hi everyone!
Currently I'm developping a vocoder algorithm that must run at a
certain speed
on the DSP.
After having updated my code and having optimized as much as I could,
I found out
that memory could be configured in a 2-way cache associative.
Namely:
I have configured the DSP with this file .cmd:
-c /* 14 ROM model.. */
-m boot.map
--stack_size=4096
/* SPECIFY THE SYSTEM MEMORY MAP */
MEMORY
{
L2_BOOT : origin = 0x107F8000, length = 0x000020 /* 20 bytes for
BOOT CODE */
L2 : origin = 0x107F8020, length = 0x017Fe0 /* nearly 96kB
program or data RAM */
L1P : origin = 0x10E00000, length = 0x004000 /* 16kB program RAM */
L1P_cache : origin = 0x10E04000, length = 0x004000 /* 16kB cache
program RAM */
L1D : origin = 0x10F04000, length = 0x014000 /* 48kB data RAM */
}
/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
SECTIONS
{
.etext: {} > L2_BOOT
.text >> L1P | L2 align=32
.cio: {} > L2 align=32
.switch: {} > L2 align=32
GROUP > L1D
{
.comm2arm_mem_sect: align=32
.epdebug : align=32
.shared_mem_sect : align=32
.bss align=32
.const: {} align=32
.far: {} align=32
.cinit: {} align=32
}
.sysmem > L1D align=32
GROUP > L1D (HIGH)
{
.stack_protection_sect
.stack
}
}
//