Can MikroElektronika eth click work with BBB

Hello

I’m trying to get the eth click board from MikroElektronika to work on a BBB but I fail. I can see that others successfully have used it on a PocketBeagle but I’m running on a BBB industrial.

To fit the board I use the mikroBUS cape and I use slot 1 on the cape.
The Debian image from 2018-03-05 is used.

The file /boot/uEnv.txt has been modified with:

enable_uboot_overlays=1

I have done some more trials to get this working , but still no luck.
I have written a new device tree file BB-mBUS_3_eth_click-00A0.dts, listed in the end of this post. This time I wrote it for slot 3 on the cape.
This slot use the other SPI port (spi0 instead of spi1 that is on slots 1,2,4).

My new questions are:

  1. Do I have to do anything else than modifying the file /boot/uEnv.txt once the dts/dtbo file is correct to get a “eth click” board working?
  2. Can anyone tell me if I’m doing the interrupt configuration correct in the attached source file? (I don’t know the syntax for this)
  3. Anything else that is wrong anyone can point out?

/*

  • Copyright © 2017 Robert Nelson

OK, I’m making progress.
By modifying the dts file (mostly trial and error) I now have something that works even if there are still issues.

Just like in another post there is a 90s delay during boot. Also the original eth0 (on BBB) is renamed to rename3.
Anyone got any ideas on what’s going on there?

Here is the dts that got me this far. If I get the slot 1 version to work I will post that too.

/*

  • Copyright © 2017 Robert Nelson

You might need to add an alises:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/am33xx.dtsi?h=v4.18-rc2#n22

ethernet2 = &enc28j60;

Regards,

Okay, this took a few more hacks..

Disable:

/etc/udev/rules.d/70-persistent-net.rules

Remove the net option from /boot/uEnv.txt

Then got it working..

https://github.com/beagleboard/bb.org-overlays/blob/master/src/arm/BB-mBC1-ETH-CLICK.dts

I'll work on adding it to 2/3/4 with full pin doc's so we can easily
port more clicks..

Regards,

and this was on v4.18-rc2..

Regards,

Thank you very much Robert!

Here are my results testing with your new overlay and configuration changes:
I tried it first on my board with the image Debian 9.3 2018-03-05 but it did not work.
Then I tried Debian Buster 2018-06-17 and it worked.
Next I selected the image that I will continue with, Debian 9.4 2018-06-17. It worked on that too.

I’m not sure about what net option you suggested to remove from /boot/uEnv.txt
I tried with this change:

cmdline=coherent_pool=1M quiet
#cmdline=coherent_pool=1M net.ifnames=0 quiet

both worked, however boot time was 10s faster with the original line.

The removal of data in /etc/udev/rules.d/70-persistent-net.rules was needed.

Thank you very much Robert!

Here are my results testing with your new overlay and configuration changes:
I tried it first on my board with the image Debian 9.3 2018-03-05 but it did
not work.
Then I tried Debian Buster 2018-06-17 and it worked.
Next I selected the image that I will continue with, Debian 9.4 2018-06-17.
It worked on that too.

There was some kernel backports to support the ETH device, just make
sure you have the latest kernel and u-boot overlays enabled..

I'm not sure about what net option you suggested to remove from
/boot/uEnv.txt
I tried with this change:
cmdline=coherent_pool=1M quiet
#cmdline=coherent_pool=1M net.ifnames=0 quiet
both worked, however boot time was 10s faster with the original line.

The removal of data in /etc/udev/rules.d/70-persistent-net.rules was needed.

So far it looks like removing
/etc/udev/rules.d/70-persistent-net.rules is enough..

Kinda went crazy this afternoon, added ETH & ETH-WIZ support to spots 2, 3, 4.

You can install both ETH & ETH-WIZ into any location. (i only have one
of each, so couldn't test more..)

Slot 1,2,4: share one spi bus..
Slot 3: SPI: make sure to unsolder/solder J7/J8 on back, it's also the
only slot with it's own spi bus.. (You'll lose TX/RX on Slot 1)
Slot 4: This has a non-hardware CS pin (gpio-cs), thus no DMA avaiable.

Regards,