Hello everybody,
I have been trying to change my clock selection for the L3 and L4
interconnects. On page 444 of the "SPRUF98F" from Texas Instruments,
there is on Table 4-145. CM_CLKSEL_CORE, physical address 0x4800 4A40
the possibility of changing the bits 0:1 for CLKSEL_L3 and bits 2:3
for CLKSEL_L4.
When I start my board, there are set to "1010" which means both are
divided by 2. I would to have both as divided by 1. However, 0x1 for
both means Reset and when I try to set them like that, my board stop
responding. Furthermore, it is written for CLKSEL_L4:
0x1: L4_CLK is L3_CLK divided by 1 (boot mode only).
Any suggestions would be apprecciated,
Frederico Lima