Hello,
all the examples I’ve seen for pru uses the syntax of LBBO (and SBBO, …) like this:
SBBO r0, r1, 0, 4
but when I try to compile this by clpru compiler
void start_adc_ch1(void)
{
asm volatile
(
//Init ADC CTRL register to enable step editing
" LDI32 r8, 0x44E0D040 \n"
" LDI32 r9, 0x00000004 \n"
" SBBO r9, r8, 0, 4 \n"
//Enable ADC STEPCONFIG 1
" LDI32 r8, 0x44E0D054 \n"
" LDI32 r9, 0x00000003 \n"////ch1 enabled + ts enabled
" SBBO r9, r8, 0, 4 \n"
//Init ADC STEPCONFIG 1
" LDI32 r8, 0x44E0D064 \n"
" LDI32 r9, 0x00000004 \n" //single shot + averaging 2
" SBBO r9, r8, 0, 4 \n"
//enables ADC
" LDI32 r8, 0x44E0D040 \n"
" LDI32 r9, 0x00000001 \n"
" SBBO r9, r8, 0, 4 \n"
);
}
it gives me the following errors:
“/tmp/01134q33McW”, ERROR! at line 49: [E0003] Invalid instruction
SBBO r9, r8, 0, 4
“/tmp/01134q33McW”, ERROR! at line 52: [E0003] Invalid instruction
SBBO r9, r8, 0, 4
“/tmp/01134q33McW”, ERROR! at line 55: [E0003] Invalid instruction
SBBO r9, r8, 0, 4
“/tmp/01134q33McW”, ERROR! at line 58: [E0003] Invalid instruction
SBBO r9, r8, 0, 4
if I add “&” before the first argument (SBBO &r9, r8, 0, 4) it works fine and seems to be working.
what is the reason of such behavoir?
ps: TI’s wiki allow both types of addressing and it says both types are eual. ( http://processors.wiki.ti.com/index.php/PRU_Assembly_Instructions#Store_Byte_Burst_.28SBBO.29 )