Configuring P9-41 and P9-42 in Cape EEPROM

Hi! I’m new here. I’ve just made my first BBB cape for a contraption I’m building at the day job. I’m currently at the “confused about cape EEPROMs and device tree overlays” stage, as is tradition.

I’m using the two PRU I/Os assigned to header pins P9-41 and P9-42 as wire-or alternate options. The BBB SRM lists cape EEPROM offsets for configuring the CLKOUT2 and GPIO0_7 pins, which I’ll need to configure as inputs so that I can use the alternative GPIO3_20 and GPIO3_18 pins for PRU stuff. But I don’t see offsets defined for GPIO3_20 or GPIO3_18, so how can I configure them in my cape’s EEPROM?

One of the things I’m confused about is whether the pin definitions in the cape EEPROM even get used by anything. Does the default Debian distribution for the BBB pay any attention to the pin definitions in a cape’s EEPROM? Does it just use the board name and version found in the EEPROM to locate a matching device tree overlay, and ignore the rest of the EEPROM? Or something else entirely?

I’d appreciate any hints on this stuff.