Hi.
I’m not sure that is the exact place to ask, but…
I’m trying to connect an external NAND to the GPMC pins. I updated the device tree for that, and the NAND is identified correctly.
Yet, later during the nand init, the partitions, as defined in the device tree, are not created.
I used to the same partitions definition on a different AM335x board, which used kernel version 3.x, while BBB uses now 4.14.x, and the NAND support code was changed a lot.
My device tree looks quite fine, as much as I can tell (see below).
Again, the nand works, it is being identified, all signals work correctly (had to remove one of the MMC’s for that). the issue is linux creating partitions.
does any one have any clue about it?
`
&am33xx_pinmux {
bbcape_nand_flash_pins: bbcape_nand_flash_pins {
pinctrl-single,pins = <
0x00 (MUX_MODE0 | PIN_INPUT_PULLUP) /* gpmc_ad0.gpmc_ad0 /
0x04 (MUX_MODE0 | PIN_INPUT_PULLUP) / gpmc_ad1.gpmc_ad1 /
0x08 (MUX_MODE0 | PIN_INPUT_PULLUP) / gpmc_ad2.gpmc_ad2 /
0x0c (MUX_MODE0 | PIN_INPUT_PULLUP) / gpmc_ad3.gpmc_ad3 /
0x10 (MUX_MODE0 | PIN_INPUT_PULLUP) / gpmc_ad4.gpmc_ad4 /
0x14 (MUX_MODE0 | PIN_INPUT_PULLUP) / gpmc_ad5.gpmc_ad5 /
0x18 (MUX_MODE0 | PIN_INPUT_PULLUP) / gpmc_ad6.gpmc_ad6 /
0x1c (MUX_MODE0 | PIN_INPUT_PULLUP) / gpmc_ad7.gpmc_ad7 /
0x70 (MUX_MODE0 | PIN_INPUT_PULLUP ) / gpmc_wait0.gpmc_wait0 /
0x74 (MUX_MODE0 | PIN_OUTPUT_PULLUP) / gpmc_wpn.gpmc_wpn /
0x7c (MUX_MODE0 | PIN_OUTPUT_PULLUP) / gpmc_csn0.gpmc_csn0 /
0x90 (MUX_MODE0 | PIN_OUTPUT) / gpmc_advn_ale.gpmc_advn_ale /
0x94 (MUX_MODE0 | PIN_OUTPUT) / gpmc_oen_ren.gpmc_oen_ren /
0x98 (MUX_MODE0 | PIN_OUTPUT) / gpmc_wen.gpmc_wen /
0x9c (MUX_MODE0 | PIN_OUTPUT) / gpmc_be0n_cle.gpmc_be0n_cle */
;
};
};
&elm {
status = “okay”;
};
&gpmc {
status = “okay”;
ranges = <0 0 0x01000000 0x10000000>; /* address range = 16MB (minimum GPMC partition) /
nand@0,0 {
compatible = “ti,omap2-nand”;
reg = <0 0 4>; / device IO registers /
pinctrl-names = “default”;
pinctrl-0 = <&bbcape_nand_flash_pins>;
ti,nand-ecc-opt = “bch8”;
ti,elm-id = <&elm>;
/ generic bindings /
nand-bus-width = <8>;
/ vendor specific bindings /
gpmc,device-width = <2>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <80>;
gpmc,cs-wr-off-ns = <80>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <80>;
gpmc,adv-wr-off-ns = <80>;
gpmc,we-on-ns = <20>;
gpmc,we-off-ns = <60>;
gpmc,oe-on-ns = <20>;
gpmc,oe-off-ns = <60>;
gpmc,access-ns = <40>;
gpmc,rd-cycle-ns = <80>;
gpmc,wr-cycle-ns = <80>;
gpmc,wait-pin = <0>;
gpmc,wait-on-read;
gpmc,wait-on-write;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/ MTD partition table */
/* All SPL-* partitions are sized to minimal length
- which can be independently programmable. For
- NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = “NAND.SPL”;
reg = <0x00000000 0x00040000>;
};
partition@1 {
label = “NAND.SPL.backup1”;
reg = <0x00040000 0x00040000>;
};
partition@2 {
label = “NAND.SPL.backup2”;
reg = <0x00080000 0x00040000>;
};
partition@3 {
label = “NAND.SPL.backup3”;
reg = <0x000c0000 0x00040000>;
};
partition@4 {
label = “NAND.u-boot-spl-os”;
reg = <0x00100000 0x00080000>;
};
partition@5 {
label = “NAND.u-boot”;
reg = <0x00180000 0x00100000>;
};
partition@6 {
label = “NAND.u-boot-env”;
reg = <0x00280000 0x00040000>;
};
partition@7 {
label = “NAND.u-boot-env.backup1”;
reg = <0x002c0000 0x00040000>;
};
partition@8 {
label = “NAND.kernel”;
reg = <0x00300000 0x00700000>;
};
partition@9 {
label = “NAND.file-system”;
reg = <0x00a00000 0x1f600000>;
};
};
};
`