I need some help understanding legacy PRU code written in assembly. What exactly is the address represented by C4 (0x0002_6000)? It seems that this code is setting the fourth bit starting from bit 4 of the PRU CFG to zero. But what is the PRU CFG, exactly? I’ve been starting at TI documentation and I have not been able to figure it out.
Here is the code:
LBCO r0, C4, 4, 4
CLR r0, r0, 4
SBCO r0, C4, 4, 4
From limited project documentation it seems that this is meant to enable OCP, which changes how the PRUs interact with specific pins. Would this change how I would set my PRU related pins using config-pin?
I am using a Debian Bullseye IoT 2023-09-02 Linux distribution.
Hmm. Thanks! I ~think~ that most of the information about enabling UIO is not needed anymore, and that you only need to enable UIO in uEnv.txt. At least, that seems to work for me and I can at least run assembly code on the PRU that way. The relevant section from that website is here:
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This enables the OCP Master Ports. It’s equivalent to the bit-clearing assembly instruction combination found often:
To grab some quotes from the PRU-ICSS Reference guide:
“Similar to the previous generation, the PRUs have access to all resources on the SoC through the Interface/OCP master port, and the external host processors can access the PRU-ICSS resources through the Interface/OCP Master port. The Switched Central Resource (SCR) connects the various internal and external masters to the resources inside the PRU-ICSS. The INTC handles system input events and posts events back to the device-level host CPU.”
And from Section 3.1.2 of the PRU-ICSS Reference guide:
“The PRU accesses the external Host memory map through the Interface/OCP Master port (System OCP_HP0/1) starting at address 0x0008_0000. By default, memory addresses between 0x0000_0000 – 0x0007_FFFF will correspond to the PRU-ICSS local address in Table 5. To access an address between 0x0000_0000–0x0007_FFFF of the external Host map, the address offset of –0x0008_0000 feature is enabled through the PMAO register of the PRU-ICSS CFG register space.”
So if I want to access memory outside of the range 0x0000_0000 – 0x0007_FFFF from the PRU, I need to enable OCP. I suppose that enabling OCP doesn’t change anything about interacting with the pins then.