DDR2 MT47H128M16RT25E config

[Li926744]

Hi all

I review the code from

http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/include/asm/arch-am33xx/ddr_defs.h;h=2278358ab200ecc26fc7500e01b11268fe7d43f5;hb=HEAD#l29

Here
#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332

https://raw.github.com/CircuitCo/BeagleBone-RevA5/master/BeagleBone_revA5_SCH.pdf

A5 board use 256M ddr2 with MT47H128M16 on 16bit

And from

http://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/DDR2/2Gb_DDR2.pdf

256M DDR2 only have 14 raw address

Ti Reference manual say

This 332 mean use 15 ROW

It should be 0x418052d2

right ?

Why BB a5 board can run so stable ?

[Vaibhav_Bedia]

Now this is odd. Care to post it to
http://e2e.ti.com/support/arm/sitara_arm/default.aspx ?

[Li926744]

Post it on
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/312683.aspx

[Vaibhav_Bedia]

Post it on
beaglebone A5 ddr2 config - Processors forum - Processors - TI E2E support forums

Just to close the loop here. As clarified on E2E the configuration in U-Boot
is correct.