Debugging on Windows with SoftConsole or other (free/cheap) debugger?

BeagleV
1

Installed the latest Microchip tooling on Windows (Libero SoC 2025.1 + SoftConsole 2022.2).
Programmed the fabric from Libero with a FlashPro5 without issues.
However, SoftConsole would not connect to the MPFS025 due to unexpected JTAG ID. See the log below.
Is there a fix for this issue? What other tool would work with this device? Or is there a better solution on Linux? I don’t need Linux on the chip, all will be bare-metal. Thanks!

xPack OpenOCD (Microchip SoftConsole build), x86_64 Open On-Chip Debugger 0.10.0+dev-00859-g95a8cd9b5-dirty (2022-03-15-14:08)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
MPFS
Info : only one transport option; autoselect ‘jtag’
Info : Hardware thread awareness created
do_board_reset_init
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : No Embedded FlashPro6 (revision B) devices found
Info : clock speed 6000 kHz
Info : JTAG tap: mpfs.cpu tap/device found: 0x0f8531cf (mfg: 0x0e7 (GateField), part: 0xf853, ver: 0x0)
Warn : JTAG tap: mpfs.cpu UNEXPECTED: 0x0f8531cf (mfg: 0x0e7 (GateField), part: 0xf853, ver: 0x0)
Error: JTAG tap: mpfs.cpu expected 1 of 15: 0x0f8581cf (mfg: 0x0e7 (GateField), part: 0xf858, ver: 0x0)
Error: JTAG tap: mpfs.cpu expected 2 of 15: 0x0f8781cf (mfg: 0x0e7 (GateField), part: 0xf878, ver: 0x0)
Error: JTAG tap: mpfs.cpu expected 3 of 15: 0x0f8771cf (mfg: 0x0e7 (GateField), part: 0xf877, ver: 0x0)
Error: JTAG tap: mpfs.cpu expected 4 of 15: 0x0f8181cf (mfg: 0x0e7 (GateField), part: 0xf818, ver: 0x0)
Error: JTAG tap: mpfs.cpu expected 5 of 15: 0x0f8381cf (mfg: 0x0e7 (GateField), part: 0xf838, ver: 0x0)
Error: JTAG tap: mpfs.cpu expected 6 of 15: 0x0f83c1cf (mfg: 0x0e7 (GateField), part: 0xf83c, ver: 0x0)
Error: JTAG tap: mpfs.cpu expected 7 of 15: 0x0f8191cf (mfg: 0x0e7 (GateField), part: 0xf819, ver: 0x0)
Error: JTAG tap: mpfs.cpu expected 8 of 15: 0x0f8391cf (mfg: 0x0e7 (GateField), part: 0xf839, ver: 0x0)
Error: JTAG tap: mpfs.cpu expected 9 of 15: 0x0f83d1cf (mfg: 0x0e7 (GateField), part: 0xf83d, ver: 0x0)
Error: JTAG tap: mpfs.cpu expected 10 of 1: 0x0f81a1cf (mfg: 0x0e7 (GateField), part: 0xf81a, ver: 0x0)
Error: JTAG tap: mpfs.cpu expected 11 of 1: 0x0f83a1cf (mfg: 0x0e7 (GateField), part: 0xf83a, ver: 0x0)
Error: JTAG tap: mpfs.cpu expected 12 of 1: 0x0f83e1cf (mfg: 0x0e7 (GateField), part: 0xf83e, ver: 0x0)
Error: JTAG tap: mpfs.cpu expected 13 of 1: 0x0f81b1cf (mfg: 0x0e7 (GateField), part: 0xf81b, ver: 0x0)
Error: JTAG tap: mpfs.cpu expected 14 of 1: 0x0f83b1cf (mfg: 0x0e7 (GateField), part: 0xf83b, ver: 0x0)
Error: JTAG tap: mpfs.cpu expected 15 of 1: 0x0f83f1cf (mfg: 0x0e7 (GateField), part: 0xf83f, ver: 0x0)
Error: Trying to use configured scan chain anyway…
Warn : Bypassing JTAG setup events due to errors
Info : datacount=2 progbufsize=16
Info : Disabling abstract command reads from CSRs.
Info : Core 0 could not be made part of halt group 1.
Info : Examined RISC-V core; found 5 harts
Info : hart 0: XLEN=64, misa=0x8000000000101105
Info : hart 1: currently disabled
Info : hart 2: currently disabled
Info : hart 3: currently disabled
Info : hart 4: currently disabled
Info : datacount=2 progbufsize=16
Info : Disabling abstract command reads from CSRs.
Info : Core 1 could not be made part of halt group 1.
Info : Examined RISC-V core; found 5 harts
Info : hart 0: currently disabled
Info : hart 1: XLEN=64, misa=0x800000000014112d
Info : hart 2: currently disabled
Info : hart 3: currently disabled
Info : hart 4: currently disabled
Info : datacount=2 progbufsize=16
Error: unable to halt hart 2
Error: dmcontrol=0x80020001
Error: dmstatus =0x00030c82
Error: Fatal: Hart 2 failed to halt during examine()
Assertion failed: r->is_halted, file /Host/home/vagrant/Work/openocd-0.10.0-14/openocd-softconsole-src/src/target/riscv/riscv.c, line 3198
fpServer v17 waiting for incoming connections on the port 3334 with API v5
Info : 1 1756401334137 microsemi_flashpro_server.c:1751 microsemi_flashpro_initialize() FlashPro ports available: S201541SDD
Info : 2 1756401334137 microsemi_flashpro_server.c:1752 microsemi_flashpro_initialize() FlashPro port selected: S201541SDD

2

LInux is what all the serious players are running.

Also keep in mind so much of the stuff that is out there is lame software. It will let you go so far then you find out that functionality you require to make your product a real success is held back.

This is the industry paradigm, you need to fine tune your nose and when the product smells don’t touch it. A fine example is GPU license, for one. If your UI looks like crap your product is not going to sell, hence they hold back on the license. After so many hours and big dreams of a working product your only option is the call the source and PAY THEM for a solution, see how this works…

I don’t have a solution for your problem, just wanted to share with you how the BS works with this stuff.

3

Libero SoC and SoftConsole work fine with the previous generation (SmartFusion2) and with the fabric of the PolarFire SoC. Have been using this toolchain for many years by now without issues.
There is either something wrong with the BeagleV-Fire that prevents SoftConsole from connecting, or there is a bug in SoftConsole or OpenOCD. I guess I’ll log a ticket for Microchip support.
Just weird that noone tried this yet…

4

Answering my own question:

SoftConsole works fine if I start OpenOCD externally, with exactly the same parameters and configuration file as SoftConsole would use. Interesting, might be a bug in SoftConsole?

Debugging with VS Code and the Cortex-Debug extension also works (yes, despite the name it can debug RISC-V). Here is the relevant part from the launch config:
“openOCDPreConfigLaunchCommands”: [
“set DEVICE MPFS”,
],
“postLaunchCommands”: [
“thread apply all set $pc=_start”
],
“configFiles”: [
“c:/Microchip/SoftConsole-v2022.2-RISC-V-747/openocd/share/openocd/scripts/board/microsemi-riscv.cfg”
],

Good luck.