Direct PRU pins available?

Was curious how many PRU pins (on each PRU) would be available for direct mapping to R30/R31 of the PRU? One of the drawbacks I have with the BBB is the limited direct access pins for output on both PRUs (after you use the FLASH and a few peripherals).

This board looks like it might be a really nice package.

That is covered in the SRM.


I've got a pinout spreadsheet color-coded with PRU I/O (and GPIO bank
numbers and other useful info) in github:

If you're wanting to do output, you can use standard GPIO pins (accessed
via the internal SoC L4_PERport1 bus) for all but the most timing
sensitive applications. The writes get posted so they don't stall the
PRU unless you do a bunch of them back-to-back, and the total latency is
only around 100 ns. I've got timing details from tests I ran in some
code comments:

For inputs, you really *DO* want to use the direct PRU pins, as it takes
about 165 nS to read from a GPIO register via the SoC fabric, vs one 5
nS PRU clock for the direct inputs.

But that is the BBB isn’t it? (I have used that). Was curious about the X15.

But that is the BBB isn’t it? (I have used that). Was curious about the X15.

Knowing Gerald, he isn’t going to talk about this until after the BeagleBoard-X15 is released in Feb, 2015.


There is some data publicly available for the X15 processor:

...but the info I posted earlier was for the BeagleBone and the AM335x,
as it wasn't clear (to me) you were asking about the X15.

As for how many PRU pins will be available (pinned out to accessible
connectors), that depends on the schematic which isn't available yet.