What is the expected workflow for creating, simulating, and testing HDL files?
This is what I have working right now:
I copy gateware/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE.
I modify my copy to be CUSTOM_FPGA.
Update references in the ADD_CAPE.tcl script.
Execute the build-bitstream.py script to build the Libero project.
Go into the ‘work’ directory and open the Libero project.
Create my custom HDL, wire it up, etc.
Then manually copy the HDL files back into gateware/sources/FPGA-design/script_support/components/CAPE/CUSTOM_FPGA.
Re-run build-bitstream.py and test on the board.
Since build-bitstream.py wipes out the work directory during init, I lose my project every time I test it on the board.
I have been able to create a project via command line using the libero SCRIPT:... command which seems like it should be the way to go. However, when I go this route the documentation isn’t clear on how to plug my project back into the ‘build-bitstream.py’ script so it will bake in HSS and the overlays.
Can I create a standalone FPGA project with the ‘libero SCRIPT…’ in a local/remote git repository and then have the ‘build-bitstream.py’ reference that as a source? If so, how would I do it?
I am still not quite sure what the vision for the new user experience is or if my process so far is anything close to it. That being said, I have created a script to automate some of the new cape creation processes I have been working with.
Feedback, constructive criticism, and contributions are welcome. I am happy to contribute the script back to the project as well but I haven’t found any contributing guidelines for that process.
Hello, my name is Seth. Although I am very new to verilog and hdl and the BeagleV-Fire type of FPGA, I have noticed that you are looking to contribute…
I cloned the repo with my personal account on gitlab under openbeagle.org . Also, if you look here, Sign in · GitLab , it will show you some guidelines for contribution.
Again, that is my personal build of the docs and not what gets ported to the docs.beagleboard.org online unless I make a successful merge with openbeagle.org .
Seth
P.S. I found this online: BeagleV-Fire · GitLab . Outside of the contribution link posted, I bet using the beaglev-fire link will allow for merge requests to be sent in via git.
The part you need to add to your flow is copy the VERILOG_TEMPLATE into your own folder under CAPE. Then create another build option YAML file under gateware/build-option modifying the “build-args” entry to specify your cape design as option. Looks at robotics.yaml for a syntax example. Let’s say you put your cape gateware into CAPE/CUSTOM_FPGA then use:
build-args: “CAPE_OPTION:CUSTOM_FPGA”
Thank you Seth for the information on contributing! I will try to get a fork going tomorrow.
And thank you Vauban! I was only aware of the documentation on docs.beagleboard.org and had no idea that newer information was available on docs.beagleboard.io. The link you provided is super helpful and would have saved me a ton of work. I did create a python script to automate the steps you described and I will see if I can get that submitted back to the community now that I know how.