Flush L1, L2 cache to RAM

I’m using DMA to transfer data from my kernel to the PRU. For that the kernel writes data to a buffer and after that sends an RPMsg to the PRU with a pointer. The PRU is then supposed to read the buffer and copy it locally for further use. Usually everything works, but on occasion the PRU reads old/only partially written data. I’ve made it so the PRU waits for some time after receiving the message from the kernel and that seemed to reduce failure. Right now I have a delay of 10M cycles and the issue is seemingly gone.

These symptoms leads me to believe that the kernel is modifying a copy of the buffer in L1 or L2 cache and only after some time it saves it back in RAM. This is obviously not ideal for DMA, since I rely on the data being there when I send my message. I was wondering if there is a way to flush (I don’t know if that’s the right word) the cache or some other way to confirm that the data is saved before tasking the PRU.

If you have other ideas why this effect occurs, I would greatly appreciate it!

Can you try forcing a memory flush:

//make sure memory is flushed before command is set to 1
__asm__ __volatile__("" ::
                         : "memory");

nope that didn’t do anything, but I’ve done more digging and have come to the conclusion that I should be doing it the writing thru the edma and not touch the cache at all.