FPGA Acceleration on BeagleV-Fire

General Discussion
1

Hello!

I’m working on a project where I aim to accelerate the YUV-RGB color space conversion using the FPGA side of the BeagleV-Fire. I am quite comfortable with Verilog, so I plan to use this HDL for the implementation.

However, I’m facing a challenge understanding how the RISC-V processor communicates with the FPGA. I would greatly appreciate a detailed explanation of this communication process, as I believe it is crucial for coordinating the conversion.

Additionally, I would like to know if it’s possible to create a project from scratch using Libero SoC and program the board directly from it, rather than cloning the repository, adding my files to the CAPE, generating the bitstream, and then updating the gateware on the board.

Any insights or guidance on these topics would be immensely helpful. Thank you in advance!

2

For the first part of your question, the processors use memory mapped address space to talk to the fabric, either via AXI (FIC0) or APB (FIC3). Both channels are industry standard busses, so you should go familiarize yourself with those, if you haven’t already.

As to the second part of your question, sure you can. Just make sure you have an FP5 so you can save yourself from a bad bitstream. Libero is an extremely powerful tool, just be aware that you’ll be diving in the deep end of the pool and it’s unlikely that you’ll be able to garner much help from most people here.

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