So after I had a nice PCB all laid out and routed I was looking at some of the GPIO I was planning to use with a voltmeter and noticed I had a lot of problems. These problems took the form of some GPIO being pulled up or down at power-up in opposition to the control signals I was planning.
1.) One case was P9_15 where the bootup condition is 1.6V??? That would hold my signal right smack in no-mans-land between high and low. Looking at the schematic I see that pin is in tug-of-war with another one that is not on the headers so I don’t understand the intention there.
2.) In another case the pin I selected was pulled low which means I would be putting invalid data on an output buffer because the /OE line is pulled low at power on unless my external pull-up was extremely strong.
3.) The worst case I found however, was the LCD control signals shared with GPIO (P8_27 - P8_30). LCD_DE and LCD_HSYNC are both driven low at boot and my design originally had those setup as BBB Inputs that would be fed from an external buffer. The moment that /SYS_RESETn went high, those buffers would be enabled and driving their outputs as well. If there is a conflict then I have a clear contention issue that could zap one or the other part. I discovered this when connecting those pins to a pull-up had no effect on the output voltage. Where they simply pulled low then my pull-up would have created a voltage divider and raised the voltage at that pin.
In these cases the HDMI framer was disabled. Is there anything that lists the pins and the default logic state that’s on them when the device boots? I also didn’t see anything that mentioned the SRM about being wary of LCD_HSYNC and LCD_DE being driven low. I looked at the schematic and there is a resistor shown on each of those signals but no indication of the value. Is that to protect from contention? If the HDMI framer is disabled should/will those pins remain driven?