Hardware modification on GPMC


I want to know the reason to add the PU resistor R110 on GPMC_WAIT0
pin. Is there an issue about the internal OMAP PU resistor ?


This was added to address some issues that were seen early on in various OMAP3 development platforms. This was carried forward into the Beagle design. The internal pullup would work, but the lower value made for a faster rise time which reduced delay n the SW.


Those issue are linked to the BeagleBoard or the OMAP3 ?
Is there an issue with the POP memory ?


This is the signal coming from the NAND device in the POP memory direct to OMAP. We found we had better performance with it in there. So, I guess you could say it is affected by both the OMAP3530 and the POP memory. You can certainly remove it and see if it affects operation in your application


Were you looking for NAND performance, or there was a problem to
solve ?
I will test the performance difference with our next board release.


The wait states were stretched out on the NAND. That made it slower. There was no “problem” to solve.