Has anyone had any success at working with devicetree for the AI-64

If anyone has been able to build a device tree for the AI-64 please let me know where you found all the information regarding a step by step. I have spent 6 hours on this and have only been able to correlate the pads to the P8 & P9 headers. Did find the spreadsheet and have the register addresses.

Found the sysconfig on Ti website however the “training” was a link to a forum post that was a few pages leading to nothing of value. Any suggestions where the actual training material for this is located would be appreciated.

Here is a link to the actual devicetree specifications.

When building the docs use the make html because the .pdf is broken. Open the index.html in a web browser that is located in the /build/html/

Update 4/11/2024:

Updated doc installation instructions for the github page:

sudo apt install sphinx-doc sphinx-common texlive \
texlive-latex-extra libalgorithm-diff-perl \
texlive-humanities graphviz python3-pip

export the paths as stated in the github page and just before using make, step into the top of the devicetree-specifications tree using:

$cd devicetree-specification 

If you don’t a makefile not found error will show up.

After it builds, open the file below in your browser.


The links are adjusted and the entire document will function properly.

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Adding sysconfig links for future reference:

TI SysConfig Docs:
SysConfig User’s Guide – SysConfig documentation

TI What is SysConfig Video (Oct 28, 2019):
Connect: What is SysConfig?

TI SysConfig Demo Video (Oct 30, 2019):
Connect: System configuration demo

TI e2e Forum post requesting better SysConfig training materials (Aug 21, 2023):
TI e2e: How to create a project using syscfg

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After reading what others are saying about this, especially true when its on the Ti forum. I would say those posting on that site are doing this 8hrs x 5days and most certainly would be way better than myself. And they are having issues…hmmmm… So what training are the Ti employees and partners getting that is not being exposed to us?

I am going to keep on seeking the missing information. Right now, it’s a low priority because we have a working setup. But, I am concerned that we may hit some serious roadblock at some point as we try to bring other SoC peripherals into the mix.

That is were I am at right now with this.

Did make some progress working with


Just opened it up as a project in CLion, then made my own branch, ran make. Just tested the overlay, it was a trivial change of the label name and the bbb booted up and reflected the change. I was under the impression it had to be native or cross compiled. That is not the case, just ran make on the x86 and copied it to the target. That simplifies this greatly. It is much easier to navigate when it is in an IDE.